Getting the highest performance out of the processor is only part of the challenge. After all, if you can’t get data on and off across the interconnect, then the overall system design fails. This is where the broad Synopsys IP portfolio comes into play. On the IP side, our deep collaboration with Arm includes Arm’s CMN-700 coherent mesh interconnect and our DesignWare Interface IP. We continue to incorporate capabilities in our IP to facilitate the highest performance functionalities. In addition, we strive to ensure that our IP solutions support the latest specifications, such as die-to-die, PCI Express® 5.0 and 6.0, DDR5, and CXL. For example, the integration between CMN-700 and Synopsys DesignWare DDR5 Controller offers end-to-end quality of service (QoS), allowing efficient data flow for optimal performance and quality of silicon.
Arm provides customers with Neoverse reference design material, along with end-to-end testing to ensure interoperability and compliance at the system level. Synopsys ensures interoperability and compliance with protocol specifications, but, most importantly, our IP maximizes performance. For example, our IP supports PCIe 6.0 at 64 GT/s, DDR5 at 6400 Mb/s, and die-to-die at 112 Gb/s. Together, these efforts help mitigate any performance bottlenecks and lower customer risks while making the final solution easier to use.
IP blocks also play an essential role in supporting chiplet architectures. Die-to-die connectivity provides the connections between chiplets in advanced multi-die chips. These disaggregated chips rely on ultra- and extra-short reach (USR/XSR) or high-bandwidth interconnect (HBI) links for inter-die connectivity with high data rates in any packaging technology. The die-to-die links in modern processing chips often need to support very high bandwidth. Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces can support the connectivity demands for high edge efficiency (amount of die edge consumed for a given bandwidth), as well as ensure reliable, power-efficient links with very low latency.
In addition, DesignWare IP is designed with capabilities specific to Neoverse use cases, so that designers can tap into the full performance of their interfaces through the Arm subsystem. For example, the Die-to-Die IP solution for XSR links implements an optimized interface to CMN-700, enabling a very low-latency CXL/CCIX link between two Neoverse interconnects located in separate dies.