Driving the Next Wave of Product and Market Innovation

Arm®-based SoC designs are driving the next wave of product and market innovation. These SoCs are architected to deliver superior connectivity, improved security, increased processing power, longer battery life, and advanced AI for next-generation products in a range of growing markets. Synopsys and Arm® have a long history of R&D collaboration, leading to solutions that enable mutual customers to accelerate their software development, co-verification of hardware and software, and quality of Arm-based designs. 

Key Benefits

Total Solutions for Key Market Segments
Design and deploy market-shaping solutions for markets such as HPC, automotive, and mobile
Proven Path to Optimized PPA
The benchmark for trustworthy, power-centric performance
Three Decades of Collaboration
Synopsys' solutions and flows deployed for Arm's most advanced designs

Arm Processor Solutions and Services

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Optimized Implementation for Arm-Based SoCs

Today, the majority of advanced SoCs based on Arm processors are designed using Synopsys solutions. Synopsys’ optimized solutions for implementation of Arm processors include: 

Arm & Synopsys

System Validation for Arm Products

Synopsys has been delivering FPGA-based prototyping systems to hardware and software engineers for more than 10 years. The HAPS® (High-performance ASIC Prototyping Systems) family of products provides an integrated and scalable hardware-software solution used by design and verification teams to improve their ASIC design schedules and avoid costly device re-spins. HAPS® supports all Arm processor cores & select Arm RealView® CoreTile Express boards

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Early SW Development, HW Design & Integration for Arm Products

Start development months before the hardware design is complete, enabling full system bring-up to occur within days of silicon availability: 

Arm & Synopsys

End-to-end Verification Solutions for Arm Designs

Arm and Synopsys collaborate to enable software development, architecture compliance and design verification of SoCs based on Arm® processors and Arm AMBA protocol interfaces. At every stage of design verification cycle starting from IP to SoC, Synopsys provides directed payload to software-driven verification solutions. 

Synopsys protocol verification solutions consisting of VIP, transactors, memory models, monitors and in-circuit speed adaptors for Arm Protocols and interconnects, enable verification engineers to build Arm SoCs and sub-systems to verify AMBA interfaces, test architectural compliance and tune the performance of interconnect and memory subsystems. To enable more rapid and productive verification of Arm-based SoCs, Synopsys and Arm have collaborated on many initiatives, including: SystemVerilog, verification methodology, simulation performance, low power verification, debug and verification IP for AMBA interconnect.

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Arm Core Hardening & Optimization Options

We offer a range of support for hardening and optimizing Arm cores:
  • QuickStart Kits for Arm Cores: If you want to implement Arm cores yourself, download our QuickStart documentation which contains scripts, constraints, and a reference guide.
  • QuickStart Implementation Service: a four week consulting engagement designed to help accelerate the development of Arm Cortex®-A55 based SoCs using Synopsys tools.
  • Arm Core Hardening and Optimization Services: Our CoreOpt Consultants work as a member of your team to help close your designs for timing, signal integrity, and power integrity, or take the entire core from RTL-to-GDSII and deliver a hard macro.

Synopsys Interface IP and VIP

Arm and Synopsys to closely align on product roadmaps and enhance Synopsys' Interface IP and Verification IP solutions with specific compute capabilities for Arm processor IP, maximizing system performance. Synopsys’ silicon-proven interface IP includes the most widely used protocols such CXL, Die-to-Die, PHYs and controllers for DDR, HBM, PCI Express®, CCIX, Ethernet, and USB. Synopsys VIP is approved for the full range of protocols from AMBA 5 CHI, AMBA AXI/ACE to APB. The VIP is extensively tested in conjunction with Arm interconnects, including the CCI and CCN family of interconnects, and includes specific test sequences, coverage points and checks targeted at verification of these interconnects. Designers can trust that Synopsys IP will be interoperable and successfully integrate into their Arm-based SoCs while minimizing risk and accelerating time to market.

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