Interview with Weikai Sun: Enhancing Custom Design Productivity with Synopsys Custom Design Platform

Synopsys Editorial Staff

Jul 09, 2021 / 5 min read

Designer’s Digest with Synopsys Custom Design Platform: How Synopsys Custom Design Platform and Custom Compiler are on the Fast Track

We sat down with Weikai Sun, vice president of engineering, Custom Design and Physical Verification Group at Synopsys to learn more about how Synopsys' end-to-end solutions are streamlining the design process and improving custom design productivity. 

Weikai Sun

Q: Welcome to Synopsys! What motivated you to join as VP of the Custom Compiler team?

Weikai Sun: I see this as a significant chance to impact a major part of the semiconductor industry. Custom designers have been stuck using the same tools for 20+ years – this flow is way overdue for change. At my previous company, I saw the momentum building for the Synopsys Custom Platform and Custom Compiler™. I was impressed by the long-term commitment Synopsys' executive leadership has made to deliver a more modern solution for analog and mixed-signal design. Synopsys has the people and technology to really make a difference, and this type of opportunity doesn’t come often. 

Q: What are the main challenges you see custom designers facing?

Weikai Sun: Three different pressures are squeezing design teams. There is specification pressure – the bar keeps getting higher for speed and bandwidth, and each new protocol brings new complexities. There is pressure from shrinking time to market – by the time you are done with your current chip, you are already late with the next one! And, there is pressure from new process technologies. Advanced node processes are not friendly for analog/RF. Each new process node is bringing new challenges – there are new rules, they have reduced headroom and noise floor, issues with reliability, such as self-heating and electromigration, etc.

One of the key issues designers face is coping with parasitics. I completed my Ph.D. under Wayne Dai at UC Santa Cruz and my research was on parasitic extraction. At that time, in the late 90s, interconnect delay was starting to dominate performance and becoming a focus for designers. Now consideration of layout parasitics is paramount – you can’t optimize a design from just the schematic. In a sense, the layout is now the schematic.

Q: Given these challenges, what is your team focused on?

Weikai Sun: Custom Compiler is going through a period of the rapid growth of our installed base.  Our focus has been on helping our customers transition – most of our users have come over from another vendor’s tool. For these customers, it is important that basic flow is solid. Beyond that, my priority is to bring additional value to customers. I’m most excited about driving more usage of our differentiated features. At my previous company I got very positive feedback on the Custom Compiler feature set from our team - I saw these productivity benefits first-hand. These features help designers work with higher efficiency and quality.  In particular, our visually-assisted layout features (such as the symbolic editor, interactive router and pattern router) and early parasitic analysis capabilities for designers are especially powerful. In fact, I would say for advanced nodes early parasitic analysis is a “must have.” 

Q: You mentioned early parasitic analysis – why is that important and what is different about what Synopsys is doing?

Weikai Sun: Designers need layout parasitics as early as possible. For early parasitic analysis, accuracy and correlation with signoff is very important; if you are not careful, you get incorrect data and make wrong decisions. Synopsys uses the StarRC™ solution for in-design analysis – the same engine we use for signoff. Using a common engine for signoff and in-design delivers the best possible accuracy and correlation. Competing solutions can suffer from a lack of accuracy, which causes trouble when trying to use them for real designs.  Another element of early parasitic analysis is our partial layout extraction flow, which allows designers to run parasitic simulations while the layout is in progress. This is a complex problem, and I think our team did a great job in creating a streamlined flow for this.

Q: You used to be part of the IP development team at Synopsys. Can you talk about how the Custom Compiler and IP development teams work together?

Weikai Sun: In the IP business, it’s important that we have the IP the customer needs on the process they are going to use – this means our IP team needs to produce 100s of IP blocks per year. Our IP team is the leading developer on the latest process nodes for the latest generation of protocols. Some implications of this is that we are working closely with the foundry as new nodes are brought on stream. Often this requires new tool features, and it always requires updates to our methodologies. Our focus was on repeatable and scalable processes. In the last 5 years, we’ve added literally thousands of new hard IP developers – and they all needed to be as productive as possible. The work with the IP group helps us  shape our tool for real users - more often than not, our customers find the value we provide from features we develop for a new node is spot on because of the work we put into enabling our IP team. We came up with the concept of a Quick Start Kit so we could deploy what we developed for our internal use into the hands of our Custom Compiler user community.

Q: What is a Quick Start Kit, and why is it important?

Weikai Sun: A Quick Start Kit (QSK) is a combination of tool settings, methodologies and utilities optimized for a specific process technology. You can’t do the most advanced nodes the same way you did 40nm, but our tools need to handle both. The difference comes from settings, new features enabled in the PDKs, some special features and even some process-specific utilities. We make these available to our customers, which can shorten the time it takes to become productive on a new node. These things are proven in production by our IP team and can make a big impact. I met with a customer recently who just finished a tapeout with the latest foundry process and they said they saw a 4X productivity gain in layout from deploying our QSK.

Advanced node design is difficult; however, some things about advanced nodes make features like template-based design more practical. Because the process is so restrictive, the layout solutions become less free form. Leading foundries are moving in that direction now – Synopsys has been ahead of the curve and we’ve been using these techniques for a while. Our experience with processes at 5nm and below is that many of these features are absolutely required – layout teams really struggle on these nodes with “traditional” tools and methods.

Q: What else would you like to share?

Weikai Sun: One thing I’m excited about is how diverse the Custom Compiler team is. We have members from very different cultures and each brings a unique value. I see an opportunity to blend these cultures and unlock the full capabilities of our team. Every one of us is motivated by the chance to displace the old generation of custom design tools. The time is right for a more modern solution – one that is suited to today’s engineers. With our strong, diverse team – I see a good chance to get there.

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