A: With smaller and smaller node geometries at 7nm and beyond, designs are becoming more wire-dominant and physical effects such as wiring delay, voltage drop, crosstalk, and process variability have become much stronger and have a significant impact on the design.
What is the impact on power?
First, wire-dominated design results in dynamic power becoming the more dominant component compared to leakage. Dynamic power is intrinsically hard to optimize for due to the linear dependence on the switching activity, which is difficult to capture accurately. For one, it takes long simulations to capture, and importing switching activity from simulation into the synthesis tool significantly complicates the design flow. Second, even if this whole process is set up, it’s not clear what type of workloads should be used to capture switching activity. Typical workloads may not account for worst-case situations and the chip may burn out in that case. But if we use worst-case loads, this might result in overdesigning of the chip.
Also, factors like process variability and voltage drops have the impact of making the power calculations more sensitive, as well as harder to estimate and optimize earlier in the design flow. They also lead to delay changes that can result in higher impact of glitches on the total power of the design. Glitch power is highly elusive and difficult to optimize for, but with the smaller geometry and more variability in delay, it is becoming a bigger part of the overall design.
Another impact of hyper-convergence is that many back-end effects are being brought up in the front end (left-shift), and we need to start thinking of the impact these have on power up-front. A classic example is concurrent clock and data, CCD, or useful skew technology that deliberately skews the clocks to registers to optimize timing. This impacts power, since it can help us use lower drive strength cells, and also spreads out the peak current spike at the clock edge. So, should you use CCD on a register to reduce power, or use multibit cells that might have a low-power footprint but will not allow clock skewing?
With hyper-convergence, different optimizations impact each other a lot more, and we need to account for multiple effects at the same time.