Visualizing Cross-Die Paths in Multi-Die Designs

With an unprecedented need for ever-increasing performance, scalability, high-yield, and heterogeneous integration, HPC, AI/ML, and automotive chip designers are turning to multi-die design architectures to deliver their demanding requirements and QoR targets. Through the advent of chiplets, heterogeneous integration, dedicated IP subsystems, and 2.5D/3D advanced packaging technology, multi-die designs have become the go-to solution for creating advanced silicon chips.

Developing a multi-die design introduces numerous additional steps and challenges from architectural specification through logical and physical design to verification and signoff. Designing in three dimensions adds complex die-to-die interconnects – logical and physical. Whether the architecture is 3D stacking, 2.5D interposers, or organic substrates, there can be millions of inter-die interconnects that must be created, assigned, debugged and validated. Ensuring that these interconnects are logically and physically correct and meet all complex inter-die design rules is very challenging.

As designs grow larger and become increasingly complex, chip designers need graphical visualizations of their designs in EDA tools. Today these include logic schematics and physical layout views. In a multi-die design, advanced visualizations are even more important as it becomes more difficult to visualize aspects of the design in three dimensions. Interconnect visualization is critical to efficiently track down, identify, and fix interconnect and cross-die related issues. Those issues can include:

• Contacting die bump or bonding pad alignment issues
• Missing/extra bumps
• Interconnect logical-physical consistency issues
• Incomplete path from backside bump to TSV to frontside bump
• Incomplete path through contacting dies

This trace view shows the following in a straightforward, easy to view graphical visualization for a signal path through a multi-die design:

• Signal net name (sa[10])
• Die name, relative placement, orientation (face up/down) and stacking order (Z level)
• The pin, bump, terminal for the cross-die signal net
• The TSV for the signal net

Figure 2 shows a signal path through SoC and HBM dies (red) on an organic substrate (blue) with an embedded silicon bridge (green).

Providing an input signal name, the Trace Viewer traces the complete signal path through all dies in the multi-die design, and displays each bump, logical pin, terminal, and TSV, displaying the path with all interconnections graphically through all dies. If a pin, terminal, or bump is missing, it is clearly indicated so designers can easily see such errors in the signal path, so they can be corrected much more easily.

For complete flexibility, engineers have control over object filtering, colorization, etc.

The Trace Viewer effectively filters out all other signals, isolating only the intended signal net, providing a clean, uncluttered view of the path. The viewer is also cross-linked with 3DIC Compiler’s Layout View and Error Browser, so that designers can select a multi-die related DRC violation, then immediately see the related net’s complete path.

In single die designs, graphical visualization tools greatly assist design engineers in identifying and debugging potential issues during development and verification. Designing multi-die packages in three dimensions not only further complicates design, but also the visualization and problem solving that involves complex signal path interconnects that can span numerous dies. Clearly, new graphical analysis capabilities are needed to make visualizations, error detection, and debug manageable, leading to increased productivity.

The Trace Viewer in 3DIC Compiler provides complete, cross-die graphical signal path visualization for selected nets, with identification of missing key components in the path and its integration with the Error browser, greatly simplifies the path to a clean, functional multi-die design. For more information visit the 3DIC Compiler web page.