Synopsys Verification IP provides the components and features needed by verification engineers to verify their SoC protocols and interfaces. It has been proven in production by hundreds of verification teams on thousands of projects to verify IP blocks, IP integration, SoC interconnect and complete SoCs. Synopsys Verification IP supports advanced SystemVerilog-based testbenches including built-in methodology support for UVM, VMM and OVM. It includes features to simplify testbench development, provide higher coverage and improve simulation runtime.
Synopsys Verification IP includes the next-generation Discovery™ Verification IP (VIP), which is written entirely in SystemVerilog, and Protocol Analyzer, the next-generation in protocol debug.