PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing 64GT/s systems. This Synopsys webinar explains how designers can overcome these challenges by accounting for PCIe 6.0 system-level co-design in pre-silicon. In addition, the Synopsys webinar highlights the importance of pre-silicon validation for overall system integration, performance and compliance.  


Listed below are the industry leaders scheduled to speak.

Madhumita Sanyal

Sr. Staff Technical Marketing Manager

Madhumita Sanyal is a Senior Staff Technical Marketing Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 16 years of experience in design and application of ASIC WLAN products, logic libraries, embedded memories, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business.

Narasimha Babu GVL

Synopsys Scientist

Narasimha Babu GVL is a Synopsys Scientist with 18+ years of experience providing protocol verification solutions for a variety of standard protocols including PCIe and CXL. Babu is a primary Synopsys representative for the Compute Express Link (CXL) Compliance Work Group and part of the DVCon India 2022 steering committee. He is also actively involved in writing and editing technical blog publications on PCIe and CXL verification.

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