Cloud native EDA tools & pre-optimized hardware platforms
We began the process of tracking the number of active design starts and tape outs as far back as 2003 with the 90nm process node. As new nodes come online, the field team at Synopsys monitors and tracks progress of all our active customer designs. Because of PrimeTime’s pervasiveness as a signoff tool and our strong Design Compiler synthesis position, we have very good visibility into the number of designs starts and tape outs that are happening at each node.
Even with the increasing complexities that come with each new node, we have observed that typically there’s a two-year duration between the peaks of the node ramp-ups. When there are more than 450 design starts at a particular node, we stop tracking numbers at that node and focus on the next node.
Currently, we are tracking active design starts and tape outs at 10/8/7nm. And, I want to make a couple observations and insights on Synopsys tool usage at these nodes.
First, Synopsys synthesis and signoff enables 98 percent of the 10/8/7nm designs. Design Compiler, PrimeTime, and StarRC are seeing pervasive usage at these nodes, and continue to fortify our strong position in synthesis and signoff.
Second, Synopsys place-and-route enables 92 percent of the 10/8/7nm designs. Customers continue to increasingly deploy IC Compiler II on their 10/8/7nm designs driven by quality-of-results (QoR) and time-to-results (TTR) gains.
At 7/8nm, we have more than 25 new customer adoptions, 50+ designs in development, and thousands of partitions that have already been taped out. Frankly, the Synopsys Fusion Design Platform is the leading platform for market-maker SoCs at 8/7nm.
Here are a few recent customer examples across different vertical segments:
Well, in summary, I’d like to emphasize that Synopsys is the leading solution of choice for our customers at advanced 10/8/7nm, as observed from real data on design starts and tapeouts. And, we continue to build on our leadership with active foundry and customer collaborations at the new 5/3nm design nodes and below.