1:1 with Sassine Ghazi

Q: To begin with, let me ask: How do you get an accurate estimate on the number of active design starts and tapeouts at advanced nodes?

Sassine Ghazi:

We began the process of tracking the number of active design starts and tape outs as far back as 2003 with the 90nm process node. As new nodes come online, the field team at Synopsys monitors and tracks progress of all our active customer designs. Because of PrimeTime’s pervasiveness as a signoff tool and our strong Design Compiler synthesis position, we have very good visibility into the number of designs starts and tape outs that are happening at each node.

Q: Any observations from your data on the node ramp-up over the years?

Sassine Ghazi:

Even with the increasing complexities that come with each new node, we have observed that typically there’s a two-year duration between the peaks of the node ramp-ups. When there are more than 450 design starts at a particular node, we stop tracking numbers at that node and focus on the next node.

Q: What are the more recent nodes that you are tracking? Any insights?

Sassine Ghazi:

Currently, we are tracking active design starts and tape outs at 10/8/7nm. And, I want to make a couple observations and insights on Synopsys tool usage at these nodes.

First, Synopsys synthesis and signoff enables 98 percent of the 10/8/7nm designs. Design Compiler, PrimeTime, and StarRC are seeing pervasive usage at these nodes, and continue to fortify our strong position in synthesis and signoff.

Second, Synopsys place-and-route enables 92 percent of the 10/8/7nm designs. Customers continue to increasingly deploy IC Compiler II on their 10/8/7nm designs driven by quality-of-results (QoR) and time-to-results (TTR) gains.

Q: Can you comment on customer adoptions at these advanced nodes?

Sassine Ghazi:

At 7/8nm, we have more than 25 new customer adoptions, 50+ designs in development, and thousands of partitions that have already been taped out. Frankly, the Synopsys Fusion Design Platform is the leading platform for market-maker SoCs at 8/7nm.

Here are a few recent customer examples across different vertical segments:

• We taped out the world’s largest 7nm CPU design with 1 billion+ instances. It was implemented 100% with IC Compiler II
• We achieved ~80% utilization on a next-generation mobile processor. And, achieving such high utilization at an early 7nm ramp-up is not easy!
• One customer attained 2GHz+ performance on their revolutionary home network and storage design
• We demonstrated 3% better area than our competition on a next-generation machine-learning processor. This was a significant win for our breakthrough Fusion Technology
• In another 7nm machine-learning/data-analytics platform design, we were able to achieve 5% better area using Design Fusion that enables logic restructuring during the place-and-route. This was both a technical and business win for us.