Synopsys Webinar | Available On-Demand

Functional ECOs are indispensable to the Silicon design process and yet they pose a big challenge to the design community. The ECO changes are made directly in the final converged netlist which differs significantly with the RTL due to optimization and convergence. Since the ECOs are done very close to tape out, these are time critical missions and any inefficiency in implementation will directly impact the cost of the product. 


An efficient automated solution is imperative in implementing the functional ECO fast, accurately and predictably. In this Synopsys webinar we will discuss functional ECO solutions including Formality Interactive ECO Flow and Formality Automated ECO flow and how they have helped in optimal patch generation and faster patch validation methods which can enable designers to meet time-to-market requirements.


Listed below are the industry leaders scheduled to speak.

Sidharth Ranjan Panda headshot

Sidharth Ranjan Panda

Engineering Manager


Sidharth Ranjan Panda is an Engineering Manager responsible for formal equivalence verification signoff, functional ECOs and UPF ECO closure for all products in HSPE Organization at Intel. 

Sidharth has 8+ years of experience in backend formal verification, functional ECO closure and low power signoff domains. He holds a Master’s Degree of Technology from BITS Pilani, India.

Avinash Palepu headshot

Avinash Palepu

Product Marketing Manager


Avinash Palepu is the Product Marketing Manager for Formality, Formality ECO and ESP products. Starting with Intel as a Design Engineer, he has held various design, AE management and Product Marketing roles in the semiconductor design and EDA industries. Avinash holds a Master’s degree in EE from Arizona State University and a Bachelor’s degree from Osmania University.

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