Functional ECOs are indispensable to the Silicon design process and yet they pose a big challenge to the design community. The ECO changes are made directly in the final converged netlist which differs significantly with the RTL due to optimization and convergence. Since the ECOs are done very close to tape out, these are time critical missions and any inefficiency in implementation will directly impact the cost of the product.
An efficient automated solution is imperative in implementing the functional ECO fast, accurately and predictably. In this Synopsys webinar we will discuss functional ECO solutions including Formality Interactive ECO Flow and Formality Automated ECO flow and how they have helped in optimal patch generation and faster patch validation methods which can enable designers to meet time-to-market requirements.