1:1 Abijeet Chakraborty

Spotlight on Design Compiler NXT

We sat down with Abhijeet Chakraborty, VP of Engineering in the Design Group, to learn more about Synopsys’ Design Compiler® NXT and how engineers are using many of the innovative technologies delivered with Design Compiler NXT to significantly improve PPA while at the same time enjoying faster runtime.

Q: Can you briefly explain what Design Compiler NXT is?

Abhijeet Chakraborty:

Design Compiler NXT which was released in March of 2019 is the latest innovation in the Design Compiler family of RTL synthesis products. Design Compiler NXT technology innovations include fast, highly efficient optimization engines, cloud-ready distributed synthesis, a new, highly accurate approach to RC estimation, and capabilities required for advanced process nodes.

Q: That sounds great how do these advances translate into benefits for the users?

Abhijeet Chakraborty:

One of the primary goals of Design Compiler NXT was to deliver faster runtimes. While of course, your mileage may vary, users should see on average a 2x speed-up with no degradation in PPA (Power, Performance, and Area). By utilizing advanced optimizations such as concurrent clock and data optimization, users will see 5-8% improvements in dynamic power and timing. Design Compiler NXT can use IC Compiler™ II placement optimization engines and using this functionality and additional improvements that we have made, users will see a 5% or more reduction in area. A 5% reduction in area is quite significant. We even had a customer switch from our competition to Design Compiler NXT for a 4% reduction in area!

Q: Earlier you mentioned “capabilities for advanced process nodes”, can you elaborate?

Abhijeet Chakraborty:

Sure! Historically, synthesis solutions did not typically have to do go through any sort of certification or enablement program for new process nodes. However, starting from around 7nm, the various foundries started introducing physical optimizations and other technologies that needed to be accounted for in synthesis. Synthesis solutions now need to meet certain criteria and functionality to be certified or enabled for a specific process node. Synopsys works very closely with our foundry partners very early in the process lifecycle to ensure this functionality is in place and certified for our mutual customers to benefit from. A good example is the recent press release that we did with Samsung Foundry to announce Design Compiler NXT certification for Samsung Foundry’s 5/4nm FinFET process technologies.

Q: Can you tell us a little more about Design Compiler NXT’s physically-aware optimizations?

Abhijeet Chakraborty:

We discussed the runtime and PPA improvements that Design Compiler NXT delivers. In addition to that, we also introduced technology to leverage IC Compiler II placement optimizations within Design Compiler NXT. These optimizations not only ensure improved correlation with IC Compiler II but deliver further improvements in area, power, and performance. Congestion and RC correlation are also significantly improved with the introduction of these new technologies. 

Q: Do you think that Design Compiler Ultra users will see a benefit adopting Design Compiler NXT?

Abhijeet Chakraborty:

Absolutely! As I discussed earlier, there will be a runtime benefit moving to Design Compiler NXT. Another important consideration is the new optimizations and physically-aware functionalities that are improving PPA. We recently had a customer migrate from Design Compiler Ultra to Design Compiler NXT due to a 3% area improvement on a significantly high-volume chip. This customer has elected to standardize on Design Compiler NXT and even other design groups that were using the competition are moving to Design Compiler NXT.

Q: What do you see are the limitations that prevent customers from achieving the best PPA with Design Compiler NXT?

Abhijeet Chakraborty:

That is an excellent question. An area that many designers may not be aware of is logic equivalence checking (LEC). Designers using 3rd party logic equivalence checking tools are being forced to switch off optimizations for those tools to successfully verify their design. Formality is the only tool in the market that can independently verify ALL of Design Compiler NXT advanced optimizations. We have countless examples of customers switching to Formality and seeing improvements in PPA by enabling aggressive Design Compiler NXT optimizations!

Q: Thank you for sharing this in-depth look into Design Compiler NXT and the many advances and benefits it delivers to users.

Abhijeet Chakraborty:

You’re welcome. Design Compiler NXT is an exciting addition to the Design Compiler family and we look forward to helping designers realize faster runtimes and improved PPA.