Frontiers in Digital and Custom Design Blog

Technologies and techniques for addressing advanced-node design challenges

Analog engineer thinking about layout effeciency

The first of this two-part post will explore the problems facing designers working on SoCs targeting energy-efficient design, and how Synopsys’ PrimeShield™ technology can help optimize designs for lower power while achieving aggressive time-to-market goals.

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Analog engineer thinking about layout effeciency

I’m always excited to hear stories from customers that are deploying advanced techniques with Custom Compiler™ to improve their productivity. 

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PrimeSim Continuum

As the HPC industry is moving towards a heterogeneous computing model, Synopsys and NVIDIA engineers have been working together to use GPUs to accelerate circuit simulation technology.

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SNUG World audience

The Artificial Intelligence (AI) track at the 2021 event offers a real mix of insights and various aspects of AI-based design, the challenges and successes, and in many cases, a much better, efficient way of incorporating strategies and methodologies. 

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SNUG World audience

We have an incredible lineup! There are 200+ technical presentations, tutorials and panels across 18 technology tracks

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monitoring sensing

We have an incredible lineup! There are 200+ technical presentations, tutorials and panels across 18 technology tracks

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monitoring sensing

Criteria for devices tested continually changes. How can you turn worst-case scenarios into best case scenarios when designing an SoC? 

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PPA targets are pre-defined values driven by multiple static metrics, including clock and data path timing, power consumption at specific voltage levels and floorplan sizes and shapes. 

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