Designer's Digest
Issue #19: Insights on Extraction for Custom Design and Advanced Nodes
Welcome to the Designer's Digest!
This issue of Designer’s Digest is focused on parasitic extraction for advanced nodes and custom design. New device architectures from gate-all-around, to vertical and complimentary FET are bringing new challenges to accurate parasitic extraction. In this issue learn about the challenges at these nodes, how the custom design market is driving new requirements for extraction tools and how Synopsys is addressing these topics.
We sat down with Mo Movahed-Ezazi, R&D Vice President for extraction technologies at Synopsys, to learn more about Synopsys StarRC™, QuickCap™, and how they can be used to address the emerging challenges around custom design and advanced nodes.
Certified Synopsys design solutions enable HPC, mobile, 5G, and AI SoCs and offer cutting-edge power savings and performance
Read NowWant to learn about new techniques available from EDA tools such as StarRC to tackle advanced node hierarchical physical design challenges from an interconnect perspective?
Watch NowSoCs for markets like 5G, biotechnology, AI, and automotive come with new challenges for parasitic extraction and design closure
Read NowEvent: Digital Design Technology Symposium, Oct 14, 2020
You will gain new insights from Synopsys R&D experts, users, and partners on integrated, end-to-end solutions being used to achieve industry leading QoR and productivity in key areas.
Video: StarRC Density Corner Value Proposition
This video explains the block density feature of StarRC along with the value proposition and typical use case.
Video: StarRC Virtual Metal Fill vs IC Validator Actual Metal Fill Positioning
Learn more about balancing the effect of metal fill on performance without sacrificing reliability.
Synopsys Webinar: Case Study: Optimize and Configure Synopsys DesignWare IP with RTL Architect
This webinar will provide a case study of how the Synopsys R&D team for DesignWare ARC EV Processor IP used RTL Architect to accelerate their IP’s time-to-market.
Synopsys Webinar: Lowering Tapeout Risks with Advanced Technology to Overcome Today’s ECO Closure Challenges
As chip designs advance to lower process nodes, they have become more and more complex and power hungry. Every ECO change can potentially become a bottleneck and influence the tape out schedule.