1:1 with Antony Fan

Q: Hi, Antony. Thanks for taking the time today. Synopsys TestMAX CustomFault, as we understand it, is targeted towards the analog fault simulation market. Can you give us an overview of what is driving the need for analog fault simulation today, especially for automotive IC applications?

Antony Fan:

The emergence of safety-critical applications for automotive has had a significant impact on the automotive electronics value chain. Since ICs are the fundamental enablers of applications such as ADAS and vehicle connectivity (V2X), they are required to adhere to more stringent automotive safety standards. As a result, IC designers are increasingly relying on systematic methods such as fault simulation (both digital and analog) to verify safety and ensure compliance with ISO 26262 standards.

Q: Does it mean that designers were using other methods before to verify safety?

Antony Fan:

Traditionally, IC designers have relied on assumptions of use (AoU), expert judgment, and highly targeted fault simulations to verify safety. In essence, they were simulating a handful of faults or “failure scenarios” and using expert judgment to qualify the rest. But this approach is not adequate for the stringent ASIC C/D automotive applications.  Hence the need for systematic fault simulation to cover a broad range of failure scenarios.

Q: Would you say then that IC functional safety is one of the primary use cases for Synopsys TestMAX CustomFault?

Antony Fan:

Automotive IC functional safety is certainly one of the primary use cases. In addition, analog fault simulation is also being used for manufacturing test coverage analysis and silicon failure analysis.

Q: Can you tell us more about the test coverage analysis application?

Antony Fan:

Sure. As you know, IP/SoC test coverage typically suffers from coverage holes due to “non-scan” logic and test-constrained paths. The coverage holes are more prominent in analog and custom digital designs because they are not “scan-friendly”. As a result, DFT engineers are beginning to use analog fault simulation to inject stuck-at-1/0 faults and other types of faults into these designs to plug these coverage holes. This use case takes on added significance given the very low defect rate requirements for automotive ICs.

Q: And how is analog fault simulation used in silicon failure analysis?

Antony Fan:

Test engineers are constantly adopting different approaches to optimize the failure analysis process due to the cost and time-to-market pressures. One such novel approach involves injecting faults into candidate circuits and correlating the simulation results to silicon data to identify failures due to MOS and interconnect opens and shorts. Such an approach can be deployed in conjunction with existing test methods to rapidly root case silicon failures at much lower costs.

Q: Great! Let’s turn our attention to Synopsys TestMAX CustomFault. Can you tell us more about the product and its value proposition for the primary use cases?

Antony Fan:

We built Synopsys TestMAX CustomFault with the singular objective of making sub-system and full-chip analog fault simulation practical because we foresaw performance, capacity, and throughput as being the primary challenges. We leveraged our best-in-class CustomSim™ and FineSim® simulation technology and built a highly differentiated feature set on top of it in partnership with automotive IC industry leaders. The result is a truly high-performance solution that can be used to simulate large transistor-level and mixed-signal designs with ease.

Q: Can you elaborate on the performance and capacity challenges in analog fault simulation?

Antony Fan:

Today’s automotive ICs are complex beasts with lots of analog, digital, and mixed-signal designs. Designs are generally bigger and more complex, and the analog-digital interdependence is significant especially for safety-related functions. As result, it is very common for engineers to run fault campaigns on a mixed-signal sub-system that includes the “analog” safety blocks and the associated “digital” safety mechanisms, necessitating the need for a high performance and high capacity simulator.

Q: But with such large mixed-signal designs, don’t you have to contend with 1000s of faults? Can you really conduct a full-blown fault simulation campaign on such designs?

Antony Fan:

Yes, running exhaustive fault simulation on large (100K+ MOS) designs is cost prohibitive. Synopsys TestMAX CustomFault features an advanced random sampling algorithm that can be used to reduce the default universe by several orders of magnitude. Designers can achieve their coverage targets with just a few 100 fault simulations using this approach.

Q: Let’s now talk about the two primary use cases. How does Synopsys TestMAX CustomFault help address some of the unique requirements of the functional safety and test coverage analysis use cases?

Antony Fan:

Our partnerships with IC industry leaders have been instrumental in developing the right feature set for these use cases. For example, the multi-testbench flow that allows users to efficiently grade multiple testbenches in an incremental fashion and the ISO 26262 metrics reporting for FMEDA were both developed in partnership with leading automotive IC vendors. There are other differentiated features, but we can probably save them for another discussion.

Q: Sure, I agree. To wrap up, can you comment on the availability of this product?

Antony Fan:

Synopsys TestMAX CustomFault was released in June of 2019. We continue to invest heavily in this product and plan to roll out new, highly differentiated technologies in the first half of 2020.