Cloud native EDA tools & pre-optimized hardware platforms
Well, strong semiconductor market drivers like autonomous driving, 5G wireless, and the adoption of artificial intelligence (AI) are pushing for larger, faster, and more energy-efficient SoCs. These next-generation, market-shaping products are demanding new innovations in EDA tools and flows, and require superior design productivity and quality-of-results.
Synopsys’ digital design tools have maintained market leadership for decades by enabling our customers to achieve the highest productivity while optimizing for best power, performance, area, and yield. As process nodes continue to advance, the device physics, yield, power, and timing performance are becoming increasingly closely related. This has moved us to think about IC design holistically, by blurring the boundaries and traditional handoffs between the various design stages and tools to enable a more optimized and integrated flow.
The Fusion Design Platform is the industry’s first AI-enhanced, cloud-ready design platform with Fusion Technology that delivers unprecedented full-flow quality-of-results and time-to-results. It is built from Synopsys’ market-leading, massively-parallel digital design tools, and augmented with innovative capabilities to tackle the escalating challenges in cloud computing, automotive, mobile, and IoT market segments.
The Fusion Design Platform redefines conventional EDA tool boundaries and transforms the design flow by sharing algorithms between several products and technologies to eliminate iterations while delivering the industry's best full-flow power, performance, and area. The fusion of best-in-class synthesis and place-and-route optimization with industry golden-signoff and design-for-test tools enables the most predictable full-flow convergence with the fewest iterations.
The Fusion Design Platform also leverages machine learning to enable additional quality-of-results and time-to-results gains by speeding up computation-intensive analyses, predicting outcomes to improve decision-making, and leveraging past learning to drive better results. In addition, a streamlined cloud-ready design environment is enabled on major public cloud providers, as well as Synopsys-hosted infrastructures.
Using the Fusion Design Platform, SoC design teams can now achieve new levels of productivity, and accelerate the next wave of semiconductor design innovation.
Design Compiler NXT builds on our Design Compiler franchise to enable synthesis below the 5-nanometer process node. Design Compiler NXT delivers faster runtimes, best-in-class correlation to IC Compiler II, and raises the quality-of-results bar even higher than what Design Compiler has already set for the industry.
I think Fusion Compiler is the new frontier for synthesis and place-and-route. It is a unique, single product that offers a bidirectional margin-less design flow to achieve the highest power, performance, and area. It is the first vertically integrated RTL-to-GDSII solution with shared engines on a common data model that delivers a fully-correlated and convergent flow.
As you know, the Design Compiler product family has been the industry leader for more than 30 years, and has delivered the greatest synthesis innovations in areas such as test, power, data-path, and physical synthesis. Design Compiler NXT is the result of a multi-year investment to develop a next-generation synthesis tool.
It builds on our leadership position with innovations that include fast and impactful optimization engines, cloud-ready distributed synthesis, more accurate RC estimation, and new capabilities to support 5-nanometer-and-below process nodes. These technologies enable 2X faster runtime, 5 percent better quality-of-results, and improved correlation with IC Compiler II.
And yes, it is 100 percent compatible with Design Compiler Graphical scripts and UI, and delivers significant new capabilities with a seamless, no-bridge-crossing upgrade from existing design flows.
Fusion Compiler is the industry’s only RTL-to-GDSII product that is architected with a single, scalable data-model, best-in-class optimization engines shared across synthesis and place-and-route, and an analysis backbone based on the industry’s golden signoff tools. We have fused together best-in-class synthesis and signoff technologies with our leading place-and-route technology. This single cockpit approach offers unmatched quality-of-results and faster throughput to address the challenges presented by the industry's most advanced designs.
Technologies previously used only in place-and-route can now be applied during synthesis, and vice versa, scaling new heights in timing, power, and area optimization. In addition, having a predictable flow from synthesis to signoff further reduces design iterations, ensuring that teams can meet their aggressive product delivery schedules.
After the first successful tapeouts, early adopters are now engaged in broadly deploying Fusion Compiler on their most advanced designs. Fusion Compiler offers them a single, unified RTL-to-GDSII optimization framework delivering a predictable flow with up to 20 percent better quality-of-results and 2X faster throughput.
I am really thrilled by the overall industry reaction, and the positive response from semiconductor companies. In fact, our market-leading customers and early adopters have already taped out some very challenging designs with our new offerings, realizing significant timing and power improvements. It is gratifying to see the compelling results achieved by these design teams, who are now experiencing fewer design iterations, eliminating ECO loops, and improving their quality-of-results and schedule goals.
In addition, we recently won two 2018 World Electronics Achievement (WEA) product-of-the-year awards for Fusion Technology in the EDA/IP category and Synopsys' Artificial Intelligence Solution in the Software/Tool category. These awards are testaments to the proven success of these game-changing innovations, and our continued collaboration with SoC innovators and market leaders.