This video explains the block density feature of StarRC along with the value proposition and typical use case.
Learn more about balancing the effect of metal fill on performance without sacrificing reliability.
This webinar will provide a case study of how the Synopsys R&D team for DesignWare ARC EV Processor IP used RTL Architect to accelerate their IP’s time-to-market.
As chip designs advance to lower process nodes, they have become more and more complex and power hungry. Every ECO change can potentially become a bottleneck and influence the tape out schedule.