Welcome to the Designer's Digest!

This issue of Designer’s Digest is focused on parasitic extraction for advanced nodes and custom design. New device architectures from gate-all-around, to vertical and complimentary FET are bringing new challenges to accurate parasitic extraction. In this issue learn about the challenges at these nodes, how the custom design market is driving new requirements for extraction tools and how Synopsys is addressing these topics. 

Webinars, Videos, and Events

Video: StarRC Density Corner Value Proposition

This video explains the block density feature of StarRC along with the value proposition and typical use case. 

Video: StarRC Virtual Metal Fill vs IC Validator Actual Metal Fill Positioning

Learn more about balancing the effect of metal fill on performance without sacrificing reliability. 

Synopsys Webinar: Case Study: Optimize and Configure Synopsys DesignWare IP with RTL Architect

This webinar will provide a case study of how the Synopsys R&D team for DesignWare ARC EV Processor IP used RTL Architect to accelerate their IP’s time-to-market.

Synopsys Webinar: Lowering Tapeout Risks with Advanced Technology to Overcome Today’s ECO Closure Challenges

As chip designs advance to lower process nodes, they have become more and more complex and power hungry. Every ECO change can potentially become a bottleneck and influence the tape out schedule.