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Welcome to the Designer's Digest!
This issue of Designer’s Digest is focused on custom equivalence checking. New custom digital flows are bringing challenges to equivalence checking since it has to handle netlist representations from Verilog behavioral model, RTL, gate, Liberty .DB, switch to transistor level. In this issue learn about the challenges, how Synopsys is addressing these topics and creating further value by incorporating various static checks along with formal equivalence checking.
1:1 with Almitra Pradhan
We sat down with Almitra Pradhan, R&D Manager for ESP technologies at Synopsys, to learn more about Synopsys ESP, and how it can be used to address the emerging challenges around custom equivalence checking & verification.
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ESP Technology
ESP’s symbolic simulation technology verifies the equivalence between reference and implementation models with high design coverage.
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VIDEO SERIES
Blog
Equivalence Checking Challenges for Low Power Design
Detecting Electrical Hazards Incurred by Inter-Voltage Domain Crossing in Custom SRAMs
Read moreThis article explains why equivalence checking is important and the difference between logic equivalence checking and sequence equivalence checking.
Learn more about Scan Testbench, IO Pads and Standard Library Verification
Model Variation And Its Impact On Cell Characterization
Learn more about new methodologies required to deal with local variation at advanced nodes.