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Welcome to the Designer's Digest!
This issue of Designer’s Digest is focused on custom equivalence checking. New custom digital flows are bringing challenges to equivalence checking since it has to handle netlist representations from Verilog behavioral model, RTL, gate, Liberty .DB, switch to transistor level. In this issue learn about the challenges, how Synopsys is addressing these topics and creating further value by incorporating various static checks along with formal equivalence checking.
ESP’s symbolic simulation technology verifies the equivalence between reference and implementation models with high design coverage.Read more
Formal Verification for Custom Digital DesignWatch now
Detecting Electrical Hazards Incurred by Inter-Voltage Domain Crossing in Custom SRAMsRead more
This article explains why equivalence checking is important and the difference between logic equivalence checking and sequence equivalence checking.
SNUG India Presentation “ESP Advanced Usage - Scan Testbench, IO Pads and Standard Library Verification”
Learn more about Scan Testbench, IO Pads and Standard Library Verification
Model Variation And Its Impact On Cell Characterization
Learn more about new methodologies required to deal with local variation at advanced nodes.