Cloud native EDA tools & pre-optimized hardware platforms
Amit Sanghani: The SLM process begins by implementing some key silicon building blocks in the form of embedded in-chip PVT monitors and structural sensors that essentially act as the eyes, ears and other senses of the device, providing deep visibility levels. This extracted silicon data is then used to calibrate design modeling parameters. Data from ring oscillator measurements, critical path test results and process/voltage/temperature (PVT) monitors are examples of this data. These data collection tools then feed the system with the raw data coupled with intelligent integration automation. Targeted analytics is then performed at each lifecycle stage to drive optimizations specific to each phase.
Amit Sanghani: SLM provides numerous benefits to not only the chip designer but also the end user of the chip. These include smoother and faster product bring-up, enhanced performance and security over the life of the chip. Other benefits include improved design performance, faster product yield ramp, higher quality yield, test time reduction and improved product quality. This in turn, means a faster time to market for the chips and systems themselves.