Enabling a Future of Advanced Node Design Where Uncertainty is a Constant

Ramsay Allen, March 1, 2021

The design of system-on-chips (SoCs) relies upon many pre-defined target parameters, including power consumption, voltage supply, clock frequency, data path timing and desired physical area. Simulation and modeling to the worst-case of such static parameters deliver probable success. However, less deterministic is how the chip will behave throughout its lifetime given that unexpected stimuli may be applied, software may be updated and workload activities may be distributed beyond the design’s original intent. To add, over time the underlying silicon manufacturing process will evolve, causing performance drift. Also, the acceptance criteria for devices tested will change. So, with certainty, we can say there will be uncertainty. The magnitude of this uncertainty will grow as geometries shrink, gate densities increase and overall design complexity progress unbounded.

monitoring sensing

Embedded Sensing Beating the Technology Curve

In-chip static measurement and real-time dynamic sensing provide insight as to the activity and behavior of the design ‘post-silicon.’ As we approach technologies of 3nm and below, the dependency upon such embedded instruments will only grow. This creates a new challenge, as sensor technology must keep up. The Power, Performance, Area (PPA) benefit of stepping down to new, smaller technology nodes will diminish unless high-quality monitoring and sensing remain available. A particular challenge for analog sensors, whose constituent components often do not improve as geometries shrink, creates a ‘running to stand still’ situation for designers.

Advanced node viability hinges on monitors’ development curve, as it has long since passed that advanced node technologies can avoid using such circuits. So, what is going to happen?

Opportunities for Silicon Assessment and In-Field Analysis

Silicon Lifecycle Management (SLM) provides a solution platform for more distributed, granular, insightful and meaningful information sources within the chip that can be utilized at stages throughout the chip’s lifetime. Right decisions are guided by good information provided. Using process, voltage and temperature (PVT) monitors alongside a new generation of performance sensors, able to provide real-time design margin analysis, will allow for the exploration of each chip for its optimal power, performance or reliability criteria.

Right now is a most interesting time for gathering embedded insights to silicon and system-level product during its lifecycle stages, from manufacture, test, packaging, deployment and eventual end of life. In a high-performance compute (HPC) context, there is more power per millimeter square of area, leading to thermal and power distribution challenges. In an automotive context, the use of relatively immature advanced node technologies for long-life, high-reliability applications where circuit aging and degradation has yet to be fully observed. Such challenges will persist and are only compounded by stacked-die packaging arrangements, for example, 2.5D, 3D and chiplets.

The lifecycle management of the product, which encompasses silicon assessment to improve design and manufacturing flows, including gathering operational data for product steering, will provide the essential tools to look beyond the horizon and continue developing compelling products for society.