The design of system-on-chips (SoCs) relies upon many pre-defined target parameters, including power consumption, voltage supply, clock frequency, data path timing and desired physical area. Simulation and modeling to the worst-case of such static parameters deliver probable success. However, less deterministic is how the chip will behave throughout its lifetime given that unexpected stimuli may be applied, software may be updated and workload activities may be distributed beyond the design’s original intent. To add, over time the underlying silicon manufacturing process will evolve, causing performance drift. Also, the acceptance criteria for devices tested will change. So, with certainty, we can say there will be uncertainty. The magnitude of this uncertainty will grow as geometries shrink, gate densities increase and overall design complexity progress unbounded.
In-chip static measurement and real-time dynamic sensing provide insight as to the activity and behavior of the design ‘post-silicon.’ As we approach technologies of 3nm and below, the dependency upon such embedded instruments will only grow. This creates a new challenge, as sensor technology must keep up. The Power, Performance, Area (PPA) benefit of stepping down to new, smaller technology nodes will diminish unless high-quality monitoring and sensing remain available. A particular challenge for analog sensors, whose constituent components often do not improve as geometries shrink, creates a ‘running to stand still’ situation for designers.
Advanced node viability hinges on monitors’ development curve, as it has long since passed that advanced node technologies can avoid using such circuits. So, what is going to happen?