Margins are of course nothing new, but as processes have shrunk, the number and scope of them has increased. In their rawest sense, margins are, in the words of Donald Rumsfeld, the “known unknowns” and the “unknown unknowns”. These are the things that we either can’t or haven’t modeled in some effective way. Nonetheless they are needed to ensure the design is reliable, manufacturable and often just as important, implementable.
Process related margins have long been the target of innovation. As we progressed from flat margining, on-chip-variation (OCV) derates through to advanced OCV derates, and more recently parametric OCV derates, we have managed to significantly reduce the amount of pessimism (and optimism!) in the cell-timing design-analysis flow. Without such advances, a growing proportion of the clock period would be lost to margin. More recently there has been innovation at Synopsys to additionally target other forms of variation – those in the wires and vias – that have again been traditionally modeled as a flat margin. By addressing such variation in a programmatic way, we are again able to free up additional scope for more optimal power, performance and area for any given design.
The second class of margins has till now had less of a focus applied to it. These are the margins that are design-flow related. Systemic margins that exist due to the way that design flows have traditionally been constructed – the point tool solution. As designs are handed off from one level of accuracy and abstraction to the next, margins are used to smooth that transition or to account for differences in the way that aspects of the design are modeled. These systemic margins not only limit the maximum achievable power, performance, and area in a similar way to process margins, but can also negatively impact design convergence and ultimately time-to-results