DesignWare DDR2/3-Lite PHY IP

Synopsys DesignWare® DDR2/3-Lite PHY IP solutions are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM memories up to 1066 Mbps data rates. Most DDR2/3-Lite PHYs support mobile DDR (LPDDR) memories. The DDR2/3-Lite PHY is an area- and feature-optimized DDR2/3 PHY that is ideal for designers who are currently implementing DDR interfaces up to 1066 Mbps and want the option of using either DDR2 or DDR3 SDRAMs. As part of the optimization of this PHY, the DDR3 write leveling feature is not supported.

The DesignWare DDR2/3-Lite PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR2/3-Lite PHY is constructed from the following libraries of components: the application-specific SSTL I/O library, a master and slave DLL library and Synopsys' unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based controller logic and the hard PHY IP.

The DDR2/3-Lite PHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching. A key component of the DesignWare DDR2/3-Lite PHY is the PHY Utility Block (PUBL) that is supplied as soft IP. The PUBL contains the circuitry to provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry (such as the at-speed loopback controller) and the DFI 2.1 interface.

DesignWare DDR Complete Solution Datasheet
DesignWare DDR2/3-Lite PHY Datasheet


  • When combined with a DesignWare DDR memory or protocol controller and Verification IP, Synopsys provides a complete DDR2/3 interface IP solution
  • Compatible with the DesignWare DDR PHY Compiler
    • GUI-based tool used to assemble a customized DDR PHY targeting a specific application
  • Scalable architecture that supports data rates from 0 up to 1066 Mbps
  • Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries
    • All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.), while simultaneously taking all the difficult timing closure out of the user's hands.
  • DFI 2.1 interface to the memory controller
  • Uses only 4 layers of metal for ITM and DLL
  • Uses only 6 layers of metal for I/O cells
  • At-speed loopback test mode for production test
  • Low latency
  • Precision analog DLLs results in ultra-low jitter
    • Master DLL component for SDRAM command generation and general host timing
    • Master/slave DLL component for SDRAM write data generation and read data capture
    • Immune to PVT variation
    • Uses core voltage level
  • Real time DQS drift detection and compensation
  • Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
  • Permits operating with SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
  • Low area and low power architecture
  • Application-specific DDR3/2 I/O library featuring PVT independent ZQ/RZQ programmable ODT and drive strength
    • Includes RTL controller logic for calibration
    • Includes power, spacer, and corner cells
  • Area optimized I/O
    • 35um I/O pitch for 65nm
    • 30um pitch for 40nm
    • Staggered I/O supported
    • Supports circuit under pad (CUP) and bond over active (BOA)
    • Supports flip chip and wire bond
  • Most DDR2/3-Lite PHYs support LPDDR SDRAMs
  • Most DDR2/3-Lite PHYs support I/O retention mode
    • Maintains I/O drive state during VDD power down
    • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
  • Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments