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DesignWare IP Prototyping Kits for DDR4/3 and LPDDR4

The DesignWare® IP Prototyping Kits for DDR uMCTL2 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS® FPGA-based prototyping system. IP Prototyping Kits are available as soft deliverables requiring various hardware prerequisites such as a HAPS system, cables, and other accessories. All IP kits include reference drivers, SoC integration logic, and application examples.

DesignWare IP Prototyping Kits for DDR4/3 and LPDDR4 Controllers

Fast DDR Controller (uMCTL2) IP Prototyping & Integration with DesignWare IP Prototyping Kits

Reduce DDR IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.

 

Highlights
Products
Downloads and Documentation
  • Supports DesignWare uMCTL2 controller
  • Includes HAPS DDR3 SODIMM HT3 (dual rank)
  • Power management, clock reset and control block
  • Software pre-installed with Linux® OS drivers
  • Pre-instrumented debug for most relevant interfaces
  • IP Prototyping Kits for DDR4/3 and LPDDR4 are available in the following configurations:
    • Soft IP Prototyping Kits for use with your in-house HAPS systems
      • DDR4/3
      • LPDDR4
Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, AXI tunnel to ARC SDPSTARs Subscribe

Description: Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, AXI tunnel to ARC SDP
Name: dwcipk_80_umctl2_fpgaphy_arc
Version: 3.80b
STARs: Open and/or Closed STARs
myDesignWare: Unsubscribe
Product Type: DesignWare Cores
Documentation:
Download: ipk_80-U-MCTL2-FPGAPHY
Product Code: B941-0


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