Synopsys IP Prototyping Kits for DDR and LPDDR
The Synopsys IP Prototyping Kits for DDR and LPDDR center around complete, out-of-the-box reference designs that consist of a validated Memory Controller IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS® FPGA-based prototyping system. IP Prototyping Kits are available as soft deliverables requiring additional hardware prerequisites such as a HAPS system, cables, and other accessories. All IP kits include reference drivers, SoC integration logic, and application examples.
Synopsys IP Soft Prototyping Kits for DDR4/3 and LPDDR4 Controllers Synopsys Soft IP Prototyping Kit for DDR5/4 Memory Controller Datasheet Synopsys Soft IP Prototyping Kit for LPDDR5/4/4x Memory Controller
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| Fast DDR Controller (uMCTL2) IP Prototyping & Integration with DesignWare IP Prototyping Kits Reduce DDR IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box. |
- Supports DDR5/4/4X, LPDDR5/4 and uMCTL2 controllers
- Power management, clock reset and control block
- Software pre-installed with Linux® OS drivers
- Pre-instrumented debug for most relevant interfaces
- IP Prototyping Kits for DDR5, DDR4/3, LPDDR5 and LPDDR4 are available in the following configurations:
- Soft IP Prototyping Kits for use with your in-house HAPS systems
- DDR5
- LPDDR5
- DDR4/3 and LPDDR4
| Soft Deliverable, IP Prototyping Kit for DWC DDR54 Controller on HAPS-100, DWC MM PHY, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for DWC LPDDR54 Controller on HAPS-100, DWC FPGA PHY, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-100, DWC FPGA DDR PHY, PCIe connection for PC | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, PCIe connection for PC | STARs | Subscribe |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-100, DWC FPGA DDR PHY, PCIe connection for PC |
| Name: | dwcipk_100_umctl2_fpgaphy_pcie |
| Version: | 3.91c |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_umctl2 |
| Product Code: | G932-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, PCIe connection for PC |
| Name: | dwcipk_80_umctl2_fpgaphy_pcie |
| Version: | 3.91c |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_umctl2 |
| Product Code: | B941-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC DDR54 Controller on HAPS-100, DWC MM PHY, PCIe connection for PC |
| Name: | dwcipk_100_ddr5_mmphy_pcie |
| Version: | 1.02a-lca00 |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_ddrctl_ddr54 |
| Product Code: | H280-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC LPDDR54 Controller on HAPS-100, DWC FPGA PHY, PCIe connection for PC |
| Name: | dwcipk_100_lpddr5_fpgaphy_pcie |
| Version: | 1.01c-lca01 |
| ECCN: | 3D991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dw_ipk_dwipk_ddrctl_lpddr54 |
| Product Code: | H281-0 |