DesignWare IP Prototyping Kits for DDR uMCTL2

The DesignWare® IP Prototyping Kits for DDR uMCTL2 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system.

With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. The prototyping kits take advantage of Synopsys’ HAPS Developer eXpress (HAPS-DX) system to provide prototyping hardware and software automation tools. Scripts and configuration files enable fast iteration.

The IP Prototyping Kits can be used as a physical target for early software bring-up, debug and test concurrently with SoC development. Out-of-the-box support for Linux software stack ensures that software developers are up and running instantly and can focus on the IP specific software (e.g., drivers, bootcode, firmware). The kits plugs into existing software tool chains and interfaces seamlessly with popular embedded software debuggers, providing system-wide debug and analysis capabilities.

DesignWare IP Prototyping Kit for DDR uMCTL2 and Emulation Gen2 multiPHY with ARC Software Development Platform

Fast DDR Controller (uMCTL2) IP Prototyping & Integration with DesignWare IP Prototyping Kits

Reduce DDR IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.

 

Highlights
Products
Downloads and Documentation
  • uMCTL2 Controller
    • DRAM data width: 32
    • Single port support
    • DDR3 mode enabled
    • 8 word burst length
    • APB clock asynchronous to core clock
  • Includes HAPS DDR3 SODIMM HT3 (single rank)
  • Power management, clock reset and control block
  • 32-bit AXI software development platform interface running at 150 MHz
  • I2C Master to allow SPD ROM access
  • Software pre-installed with Linux® OS drivers
  • Pre-instrumented debug for most relevant interfaces
  • ARC® AXS101 Software Development Platform
Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-70, DWC FPGA DDR PHY, AXI tunnel to ARC SDPSTARs Subscribe
Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, AXI tunnel to ARC SDPSTARs Subscribe
Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY, AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR3 mode, AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR4 mode, AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC DDR uMCTL2 on HAPS-DX7, Gen2 FPGA MultiPHY, AXI tunnel to ARC SDPSTARs Subscribe
IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in LPDDR4 mode, AXI tunnel to ARC SDPSTARs Subscribe

Description: IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR3 mode, AXI tunnel to ARC SDP
Name: dwipk_dx_umctl2_ddr3_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_DDR-U-MCTL2-DDR3_ARC
Product Code: HW0295-0
  
Description: IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR4 mode, AXI tunnel to ARC SDP
Name: dwipk_dx_umctl2_ddr4_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_DDR-U-MCTL2-DDR4_ARC
Product Code: HW0301-0
  
Description: IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in LPDDR4 mode, AXI tunnel to ARC SDP
Name: dwipk_dx_umctl2_lpddr4_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_DDR-U-MCTL2-LPDDR4_ARC
Product Code: HW0343-0
  
Description: IP Prototyping Kit for DWC DDR uMCTL2 on HAPS-DX7, Gen2 FPGA MultiPHY, AXI tunnel to ARC SDP
Name: dwipk_dx_umctl2_g2multphy_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_DDR-U-MCTL2-G2MultPHY_ARC
Product Code: HW0286-0
  
Description: Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-70, DWC FPGA DDR PHY, AXI tunnel to ARC SDP
Name: dwcipk_70_umctl2_fpgaphy_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: ipk_70-U-MCTL2-FPGAPHY
Product Code: B976-0
  
Description: Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, AXI tunnel to ARC SDP
Name: dwcipk_80_umctl2_fpgaphy_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_80-U-MCTL2-FPGAPHY
Product Code: B941-0
  
Description: Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY, AXI tunnel to ARC SDP
Name: dwcipk_dx_umctl2_fpgaphy_arc
Version: 3.00a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: ipk_DDR-U-MCTL2-DDR3_ARC
Product Code: C084-0