The DesignWare® IP Prototyping Kits for DDR uMCTL2 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system. The software and application examples are implemented on Synopsys’ HAPS-DX FPGA-based prototyping systems, or they can be delivered separately as files for implementation on your in-house HAPS-DX or HAPS-80 systems.
Table 1: DesignWare IP Prototyping Kits for DDR 4/3/2 & LPDDR4/3/2
Fast DDR Controller (uMCTL2) IP Prototyping & Integration with DesignWare IP Prototyping Kits
Reduce DDR IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.
Downloads and Documentation
Supports DesignWare uMCTL2 controller
Includes HAPS DDR3 SODIMM HT3 (dual rank)
Power management, clock reset and control block
Software pre-installed with Linux® OS drivers
Pre-instrumented debug for most relevant interfaces
IP Prototyping Kits for DDR and LPDDR are available in the following configurations:
HAPS-DX FPGA-based prototyping system
With ARC Software Development Platform via AXI
Soft IP Prototyping Kits
For use with your in-house HAPS-DX or HAPS-80 systems
Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-70, DWC FPGA DDR PHY, AXI tunnel to ARC SDP