The DesignWare® IP Prototyping Kits for DDR uMCTL2 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system.
With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. The prototyping kits take advantage of Synopsys’ HAPS Developer eXpress (HAPS-DX) system to provide prototyping hardware and software automation tools. Scripts and configuration files enable fast iteration.
The IP Prototyping Kits can be used as a physical target for early software bring-up, debug and test concurrently with SoC development. Out-of-the-box support for Linux software stack ensures that software developers are up and running instantly and can focus on the IP specific software (e.g., drivers, bootcode, firmware). The kits plugs into existing software tool chains and interfaces seamlessly with popular embedded software debuggers, providing system-wide debug and analysis capabilities.
Fast DDR Controller (uMCTL2) IP Prototyping & Integration with DesignWare IP Prototyping Kits
Reduce DDR IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.
Downloads and Documentation
DRAM data width: 32
Single port support
DDR3 mode enabled
8 word burst length
APB clock asynchronous to core clock
Includes HAPS DDR3 SODIMM HT3 (single rank)
Power management, clock reset and control block
32-bit AXI software development platform interface running at 150 MHz
I2C Master to allow SPD ROM access
Software pre-installed with Linux® OS drivers
Pre-instrumented debug for most relevant interfaces
ARC® AXS101 Software Development Platform
Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-70, DWC FPGA DDR PHY, AXI tunnel to ARC SDP