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DesignWare IP Prototyping Kits for DDR uMCTL2
The DesignWare® IP Prototyping Kits for DDR uMCTL2 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system. The software and application examples are implemented on Synopsys’ HAPS-DX FPGA-based prototyping systems, or they can be delivered separately as files for implementation on your in-house HAPS-DX or HAPS-80 systems.
Table 1: DesignWare IP Prototyping Kits for DDR 4/3 & LPDDR4/3
| Fast DDR Controller (uMCTL2) IP Prototyping & Integration with DesignWare IP Prototyping Kits Reduce DDR IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box. |
Highlights
Products
Downloads and Documentation
- Supports DesignWare uMCTL2 controller
- Includes HAPS DDR3 SODIMM HT3 (dual rank)
- Power management, clock reset and control block
- Software pre-installed with Linux® OS drivers
- Pre-instrumented debug for most relevant interfaces
- IP Prototyping Kits for DDR and LPDDR are available in the following configurations:
- HAPS-DX FPGA-based prototyping system
- With ARC Software Development Platform via AXI
- Soft IP Prototyping Kits
- For use with your in-house HAPS-DX or HAPS-80 systems
| Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-70, DWC FPGA DDR PHY, AXI tunnel to ARC SDP | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, AXI tunnel to ARC SDP | STARs | Subscribe |
| Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY, AXI tunnel to ARC SDP | STARs | Subscribe |
| IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR3 mode, AXI tunnel to ARC SDP | STARs | Subscribe |
| IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR4 mode, AXI tunnel to ARC SDP | STARs | Subscribe |
| IP Prototyping Kit for DWC DDR uMCTL2 on HAPS-DX7, Gen2 FPGA MultiPHY, AXI tunnel to ARC SDP | STARs | Subscribe |
| IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in LPDDR4 mode, AXI tunnel to ARC SDP | STARs | Subscribe |
| Description: | IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR3 mode, AXI tunnel to ARC SDP |
| Name: | dwipk_dx_umctl2_ddr3_arc |
| Version: | 3.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | ipk_DDR-U-MCTL2-DDR3_ARC |
| Product Code: | HW0295-0 |
| Description: | IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in DDR4 mode, AXI tunnel to ARC SDP |
| Name: | dwipk_dx_umctl2_ddr4_arc |
| Version: | 3.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | ipk_DDR-U-MCTL2-DDR4_ARC |
| Product Code: | HW0301-0 |
| Description: | IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY in LPDDR4 mode, AXI tunnel to ARC SDP |
| Name: | dwipk_dx_umctl2_lpddr4_arc |
| Version: | 3.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | ipk_DDR-U-MCTL2-LPDDR4_ARC |
| Product Code: | HW0343-0 |
| Description: | IP Prototyping Kit for DWC DDR uMCTL2 on HAPS-DX7, Gen2 FPGA MultiPHY, AXI tunnel to ARC SDP |
| Name: | dwipk_dx_umctl2_g2multphy_arc |
| Version: | 3.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | ipk_DDR-U-MCTL2-G2MultPHY_ARC |
| Product Code: | HW0286-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-70, DWC FPGA DDR PHY, AXI tunnel to ARC SDP |
| Name: | dwcipk_70_umctl2_fpgaphy_arc |
| Version: | 3.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | ipk_70-U-MCTL2-FPGAPHY |
| Product Code: | B976-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-80, DWC FPGA DDR PHY, AXI tunnel to ARC SDP |
| Name: | dwcipk_80_umctl2_fpgaphy_arc |
| Version: | 3.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | ipk_80-U-MCTL2-FPGAPHY |
| Product Code: | B941-0 |
| Description: | Soft Deliverable, IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DWC FPGA DDR PHY, AXI tunnel to ARC SDP |
| Name: | dwcipk_dx_umctl2_fpgaphy_arc |
| Version: | 3.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | ipk_DDR-U-MCTL2-DDR3_ARC |
| Product Code: | C084-0 |
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