Description: |
LPDDR4 multiPHY V2 - GF 22FDX |
Name: |
dwc_lpddr4_multiphy_v2_gf22fdx18 |
Version: |
1.20a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2022.01) ( PDF | HTML )
DesignWare Cores DDRn PHY IBIS Model Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2022.01) ( PDF | HTML )
Databooks DesignWare Cores LPDDR4 multiPHY Databook for GF22FDSOI (PHY Version: 1.20a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.45a) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY Release Notes (PHY Version: 1.20a) ( TXT )
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dwc_lpddr4_multiphy_v2_gf22fdsoi18 |
Product Code: |
D781-0 |
| |
Description: |
LPDDR4 multiPHY V2 - GF 22FDX18 for Automotive Grade 1 |
Name: |
dwc_ap1_lpddr4_multiphy_v2_gf22fdx18 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: 2019.11) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.11) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.11) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2019.11) ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY Databook for Automotive Grade 1(AP1) GF22FDX18 (PHY Version: 1.00a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.41b) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY Release Notes for Automotive Grade 1(AP1) GF22FDX18(PHY Version: 1.00a) ( TXT )
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dwc_ap1_lpddr4_mphy_v2_gf22fdx18 |
Product Code: |
E376-0 |
| |
Description: |
LPDDR4 multiPHY V2 - Intel 16 |
Name: |
dwc_lpddr4_multiphy_v2_in16 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06_sp1) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Address Mapping Application Note (Version: 1.00a) ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2020.06) ( PDF )
Designware Cores DDRn PHY ATE FirmWare Application Note (FW Version: A-2020.06_sp1) ( PDF | HTML )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for INTEL 16 (PHY Version: 1.00a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.44a) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes for INTEL 16 (PHY Version 1.00a) ( TXT )
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dwc_lpddr4_multiphy_v2_in16 |
Product Code: |
H180-0 |
| |
Description: |
LPDDR4 multiPHY V2 - SS 10LPP |
Name: |
dwc_lpddr4_multiphy_v2_ss10lpp |
Version: |
1.10a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A.2017.09) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2017.09) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Firmware ATE Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for SAMS10LPP18 (PHY Version 1.10a) ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 Utility Block Databook (PUB Version: 2.20a) ( PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes for SAMS10LPP18 (PHY Version 1.10a) ( TXT )
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LPDDR4-m-PHY-V2_SS_10LPP |
Product Code: |
C402-0 |
| |
Description: |
LPDDR4 multiPHY V2 - SS 11LPP |
Name: |
dwc_lpddr4_multiphy_v2_ss11lpp |
Version: |
1.10a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2017.09) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2018.10) ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for SAMS11LPP18 (PHY Version 1.10a) ( HTML | PDF )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.41a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes for SAMS11LPP18 (PHY Version 1.10a) ( TXT )
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LPDDR4-m-PHY-V2_SS_11LPP |
Product Code: |
D842-0 |
| |
Description: |
LPDDR4 multiPHY V2 - SS 14LPP |
Name: |
dwc_lpddr4_multiphy_v2_ss14lpp |
Version: |
2.10a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version 1.80a) ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2020.06) ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for SAMS14LPP18 (PHY Version: 2.10a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.44a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes (PHY Version: 2.10a) ( TXT )
|
Download: |
dwc_lpddr4_multiphy_v2_sams14lpp18 |
Product Code: |
C400-0 |
| |
Description: |
LPDDR4 multiPHY V2 - SS 8LPP |
Name: |
dwc_lpddr4_multiphy_v2_ss8lpp |
Version: |
1.10a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2019.04) ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for SAMS8LPP18 (PHY Version: 1.10a) ( HTML | PDF )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.42a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes for SAMS8LPP18 (PHY Version: 1.10a) ( TXT )
|
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LPDDR4-m-PHY-V2_SS_8LPP |
Product Code: |
D844-0 |
| |
Description: |
LPDDR4 multiPHY V2 - TSMC 22ULP |
Name: |
dwc_lpddr4_multiphy_v2_tsmc22ulp18 |
Version: |
1.50a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2022.01) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2022.01) D1 ( PDF | HTML )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for TSMC22ULP18 (PHY Version: 1.50a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.45a) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes (PHY Version: 1.50a) ( TXT )
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Download: |
dwc_lpddr4_multiphy_v2_tsmc22ulp18 |
Product Code: |
E001-0 |
| |
Description: |
LPDDR4 multiPHY V2 - TSMC12FFC18 |
Name: |
dwc_lpddr4_multiphy_v2_tsmc12ffc18 |
Version: |
2.70a |
ECCN: |
3E991/NLR |
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Open and/or Closed STARs |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2020.06) ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for TSMC12FFC18 (PHY Version: 2.70a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.44a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
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Download: |
dwc_lpddr4_multiphy_v2_tsmc12ffc18 |
Product Code: |
C631-0 |
| |
Description: |
LPDDR4 multiPHY V2 - TSMC16FFC18 |
Name: |
dwc_lpddr4_multiphy_v2_tsmc16ffc18 |
Version: |
3.00a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: 2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2019.04) ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for TSMC16FFC18 (PHY Version:3.00a February 2021) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.42a) ( HTML | PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes (PHY Version 3.00a) ( TXT )
|
Download: |
LPDDR4-m-PHY-V2_TSMC_16FFC |
Product Code: |
B755-0 |
| |
Description: |
LPDDR4 multiPHY V2 - TSMC28HPC+18 |
Name: |
dwc_lpddr4_multiphy_v2_tsmc28hpcp18 |
Version: |
3.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2022.01) ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2022.01) D1 ( PDF | HTML )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for TSMC28HPCP18 (PHY Version: 3.00a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.45a) ( PDF | HTML )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 for TSMC28HPCP18 Release Notes (PHY Version 3.00a) ( TXT )
|
Download: |
dwc_lpddr4_multiphy_v2_tsmc28hpcp18 |
Product Code: |
B888-0 |
| |
Description: |
LPDDR4 multiPHY V2 - TSMC28HPC18 |
Name: |
dwc_lpddr4_multiphy_v2_tsmc28hpc18 |
Version: |
1.40a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2017.07) ( PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Firmware ATE Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for TSMC28HPC18 (PHY Version 1.40a) ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 Utility Block Databook (PUB Version: 2.00b) ( PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes for TSMC28HPC18 (PHY Version: 1.40a) ( TXT )
|
Download: |
LPDDR4-m-PHY-V2_TSMC_28HPC |
| |
Description: |
LPDDR4 multiPHY V2 - UMC 28HPC+18 |
Name: |
dwc_lpddr4_multiphy_v2_umc28hpcp18 |
Version: |
1.40a |
ECCN: |
3E991/NLR |
STARs: |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2022.01) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 APB Register Map Compression Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Interconnect Signal and Power Integrity Guidelines (Version: 5.20a) Application Note ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4 multiPHY V2 coreKit User Guide (coreKit Version: A-2022.01) D1 ( PDF | HTML )
Databooks DesignWare Cores LPDDR4 multiPHY V2 Databook for UMC28HPCP18 (PHY Version 1.40a) ( PDF | HTML )
DesignWare Cores LPDDR4 multiPHY V2 PUB Databook (PUB Version: 2.45a) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4 multiPHY V2 Implementation Guide (IG Version:4.10a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4 multiPHY V2 Release Notes (PHY Version 1.40a) ( TXT )
|
Download: |
dwc_lpddr4_multiphy_v2_umc28hpcp18 |
Product Code: |
C403-0 |
| |
Description: |
LPDDR4X multiPHY - GF 14LPP18 |
Name: |
dwc_lpddr4x_multiphy_gf14lpp18 |
Version: |
1.20a |
ECCN: |
3E991/NLR |
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Open and/or Closed STARs |
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Application Notes DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY DDR4 and LPDDR4 Configuration Application Note (Version 1.10a) ( PDF )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY coreKit User Guide (coreKit Version: A-2018.10) ( PDF )
Databooks DesignWare Cores LPDDR4X multiPHY Databook for GF14LPP18 (PHY Version: 1.20a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.40a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4X multiPHY Release Notes for GF14LPP18 (PHY Version: 1.20a) ( TXT )
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LPDDR4X-m-PHY_GF_14LPP |
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Description: |
LPDDR4X multiPHY - SS 11LPP |
Name: |
dwc_lpddr4x_multiphy_ss11lpp |
Version: |
1.00a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: 2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.04) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY coreKit User Guide (coreKit Version A-2019.04) ( PDF )
Databooks DesignWare Cores LPDDR4X multiPHY Databook for SS11LPP (PHY Version: 1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.42a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4X multiPHY Release Notes for SS11LPP (PHY Version: 1.00a) ( TXT )
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LPDDR4X-m-PHY_SS_11LPP |
Product Code: |
E374-0 |
| |
Description: |
LPDDR4X multiPHY - SS 14LPP18 |
Name: |
dwc_lpddr4x_multiphy_ss14lpp18 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: 2019.11) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2019.11) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2019.11) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY coreKit User Guide (coreKit Version A-2019.11) ( PDF )
Databooks DesignWare Cores LPDDR4X multiPHY Databook for SS14LPP (PHY Version: 1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.43a) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4X multiPHY Release Notes for SS14LPP18 (PHY Version: 1.00a) ( TEXT )
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dwc_lpddr4x_multiphy_ss14lpp18 |
Product Code: |
E373-0 |
| |
Description: |
LPDDR4X multiPHY - TSMC N7 |
Name: |
dwc_lpddr4x_multiphy_tsmc7ff18 |
Version: |
3.00a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY DDR4 and LPDDR4 Configuration Application Note (Version 1.10a) ( PDF )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY coreKit User Guide (coreKit Version A-2020.04) ( PDF )
Databooks DesignWare Cores LPDDR4X multiPHY Databook for TSMC7FF18 (PHY Version: 3.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.44a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4X multiPHY Release Notes for TSMC7FF18 (PHY Version: 3.00a) ( TXT )
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dwc_lpddr4x_multiphy_tsmc7ff18 |
Product Code: |
C406-0 |
| |
Description: |
LPDDR4X multiPHY - TSMC12FFC18 |
Name: |
dwc_lpddr4x_multiphy_tsmc12ffc18 |
Version: |
3.40a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4/4X multiPHY coreKit User Guide (coreKit Version: A-2020.06) ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY DDR4 and LPDDR4 Configuration Application Note (Version 1.10a) ( PDF )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
Databooks DesignWare Cores LPDDR4x multiPHY Databook for TSMC12FFC18 (PHY Version: 3.40a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.44a) ( HTML | PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4X multiPHY Release Notes for TSMC12FFC18 (PHY Version: 3.40a) ( TXT )
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dwc_lpddr4x_multiphy_tsmc12ffc18 |
Product Code: |
C409-0 |
| |
Description: |
LPDDR4X multiPHY - TSMC16FFC18 |
Name: |
dwc_lpddr4x_multiphy_tsmc16ffc18 |
Version: |
2.20a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2018.10) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY DDR4 and LPDDR4 Configuration Application Note (Version 1.10a) ( PDF )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
Databooks DesignWare Cores LPDDR4x multiPHY Databook for TSMC16FFC18 (PHY Version: 2.20a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.41a) ( HTML | PDF )
Datasheets Synopsys DDR Complete Solution Datasheet ( PDF )
Synopsys Enhanced Universal DDR Memory and Protocol Controller IP Datasheet ( PDF )
Synopsys LPDDR4 multiPHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4x multiPHY Release Notes for TSMC16FFC18 (PHY Version: 2.20a) ( TXT )
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LPDDR4-m-PHY_TSMC_16FFC |
Product Code: |
C291-0 |
| |
Description: |
LPDDR4X multiPHY - TSMC16FFC18 for Automotive |
Name: |
dwc_ap_lpddr4x_multiphy_tsmc16ffc18 |
Version: |
2.10a |
ECCN: |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2022.01) ( HTML | PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2022.01) ( PDF | HTML )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY coreKit User Guide (coreKit Version A-2022.01) ( PDF | HTML )
Databooks DesignWare Cores AP LPDDR4X multiPHY Databook for TSMC16FFC18 (PHY Version: 2.10a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.45a) ( PDF | HTML )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores AP LPDDR4X multiPHY Release Notes for TSMC16FFC18 (PHY Version: 2.10a) ( TXT )
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dwc_ap_lpddr4x_multiphy_tsmc16ffc18 |
Product Code: |
D840-0 |
| |
Description: |
LPDDR4X multiPHY Plus - GF 12LP+18 |
Name: |
dwc_lpddr4xp_multiphy_gf12lpp18 |
Version: |
2.20a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4/4X multiPHY coreKit User Guide (coreKit Version: A-2020.06) ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
Databooks DesignWare Cores LPDDR4X multiPHY Utility Block (PUB) Addendum DDR3 Support (Version 1.00a) ( PDF | HTML )
DesignWare Cores LPDDR4XP multiPHY Databook for GF12LPP18 (PHY version: 2.20a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.44a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4XP multiPHY Release Notes for GF12LPP18 (PHY Version: 2.20a) ( TXT )
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Download: |
dwc_lpddr4xp_multiphy_gf12lpp18 |
Product Code: |
F027-0 |
| |
Description: |
LPDDR4X multiPHY Plus - GF 12LP18 |
Name: |
dwc_lpddr4xp_multiphy_gf12lp18 |
Version: |
2.30a |
ECCN: |
3E991/NLR |
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Application Notes DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY Firmware ATE Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY Firmware Training Application Note (FW Version: A-2020.06-SP1) ( PDF )
DesignWare Cores DDRn PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY APB Register Map Compression Application Note (Version:1.00a) ( HTML | PDF )
DesignWare Cores LPDDR4x multiPHY CTB and Verification (CTB Version: A-2022.11) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Interconnect Signal and Power Integrity Guidelines (Version 5.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY Training Engine Command and Address Mapping Application Note ( PDF )
DesignWare Cores LPDDR4x multiPHY coreKit User Guide (coreKit Version A-2020.06) ( HTML | PDF )
Databooks DesignWare Cores LPDDR4X multiPHY Utility Block (PUB) Addendum DDR3 Support (Version 1.00a) ( PDF | HTML )
DesignWare Cores LPDDR4XP multiPHY Databook for GF12LP18 (PHY Version: 2.30a) ( PDF | HTML )
DesignWare Cores LPDDR4x multiPHY PUB Databook (PUB Version: 2.44a) ( HTML | PDF )
Implementation Guide DesignWare Cores LPDDR4x multiPHY Implementation Guide (IG Version: 2.00a) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR4XP multiPHY Release Notes for GF12LP18 (PHY Version: 2.30a) ( TXT )
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dwc_lpddr4xp_multiphy_gf12lp18 |