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Synopsys DesignWare® LPDDR4 multiPHY IP is mixed-signal PHY IP that supplies the complete physical interface to JEDEC standard LPDDR4, LPDDR3, DDR4, and DDR3 SDRAM memories. The LPDDR4 multiPHY IP supports LPDDR4 SDRAMs up to 3200 Mbps, LPDDR3 SDRAMs up to 2133 Mbps, DDR4 SDRAMs up to 3200 Mbps and DDR3 SDRAMs up to 2133 Mbps.
DesignWare LPDDR4 multiPHY IP is assembled into a hard macro that is optimized for specific foundry nodes. Each LPDDR4 multiPHY is constructed from the following libraries of components: the application specific I/O library, one or two address/command macro block(s), multiple byte-wide data macro blocks instantiated as many times as required to accommodate the memory channel width, and separate PLL macrocells that directly abut to the address/command macro blocks and data macro blocks.
A key component of the DesignWare LPDDR4 multiPHY is the extensive in-system data training/calibration capability used to maximize the overall timing budget and improve system reliability. The DesignWare LPDDR4 multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), write leveling, and read leveling. The LPDDR4 multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR4 and LPDDR3 SDRAMs and VREF level training for LPDDR4 and DDR4 SDRAMs.  DesignWare DDR Complete Solution Datasheet
DesignWare LPDDR4 multiPHY Datasheet
- When combined with the DesignWare Enhanced DDR memory controller (uMCTL2) and verification IP, Synopsys provides a complete LPDDR4/LPDDR3/DDR4/DDR3 interface IP solution
- Support for JEDEC standard LPDDR4 and LPDDR3 SDRAMs
- LPDDR4 up to 3200 Mbps
- LPDDR3 up to 2133 Mbps
- Support for JEDEC standard DDR4 and DDR3 SDRAMs in small system configurations
- DDR4 up to 3200 Mbps
- DDR3 up to 2133 Mbps, DDR3L up to 1866 Mbps, DDR3U up to 1600 Mbps
- Support for DDR4 and DDR3 UDIMMs and RDIMMs
- Low latency
- Support for key LPDDR4 features including:
- 1.1V, ground terminated I/O for LPDDR4
- New 6-bit SDR command bus
- Data bus inversion (DBI)
- VREF training
- PoP packaging
- Independent support for power down and self refresh per rank
- Can support one or more ranks in power down or self refresh with other rank(s) active
- Fast frequency switching between individually trained frequencies
- PHY Utility Block (PUB) included as a soft IP utility that includes control features, such as data training, and provides support for production testing of the LPDDR4 multiPHY
- DFI 4.0 interface to the memory controller
- Configurable external data bus widths between 8 and 72 bits in 8-bit increments
- Permits operating with SDRAMs using data widths narrower than the compiled data width (for example, a 64-bit interface can use just 32 bits to interface to a 32-bit wide SDRAM)
- Support for 1 to 4 memory ranks
- PHY-Controller interface runs in 1:1 or 1:2 mode (ratio of application bus clock to SDRAM clock), simplifying core logic timing constraints
- 1:4 mode planned for a future enhancement
- Includes the PLL and all timing circuits necessary to meet timing specifications
- Write leveling timing circuits to compensate address and control versus data delays
- Write and read bit timing circuits compensate per-bit delay skew of individual data bits within each data byte
- Per-bit deskew of the address/command bus for LPDDR4 and LPDDR3 SDRAMs
- Locally calibrated master and slave timing circuits minimize OCV and ACLV effects and accommodate voltage or temperature change induced timing drift
- Anti-aging features help prevent effects of NBTI and HCI
- Area-optimized I/O
- Supports flip chip and wire bond
- Supports circuit under pad (CUP) and bond over active (BOA)
- I/O retention mode
- Maintains I/O drive state during VDD power down
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
- Accommodates any poly orientation in 28nm processes and below allowing the LPDDR4 multiPHY to go around a corner if required
- Advanced testability
- At-speed loopback testing on both the address and data channels
- Delay line oscillator test mode
- MUX-scan ATPG
- Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package, and printed circuit board environments
- Optional DDR PHY hardening service
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