DesignWare LPDDR4 multiPHY / LPDDR4X multiPHY IP

The DesignWare LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR4, LPDDR3, DDR4, DDR3, and/or DDR3L SDRAM interfaces operating at up to 4,267 Mbps. The DesignWare LPDDR4X multiPHY supports LPDDR4X, LPDDR4, and DDR4 SDRAM interfaces operating at up to 4,267 Mbps. With multiple interfaces, these PHYs can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 SDRAMs.

Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR4 multiPHY is provided as hardened IP components including a 4 slice Address/Command macrocell, an 8-bit data macrocell that includes DM/DBI and data strobes, and a macrocell that includes the PLL used by the PHY. The macrocells include fully integrated I/Os and are easily assembled into a variety of configurations from a single 16-bit LPDDR4 PHY to a 72-bit DDR4 PHY. An RTL-based PHY utility block (PUB) with firmware-based training capabilities supports the GDSII-based PHY.

The LPDDR4X multiPHY is a similar PHY to the LPDDR4 multiPHY that has been optimized for interfacing to lower power LPDDR4X SDRAMs that use a 0.6V nominal interface. The LPDDR4X multiPHY includes enhanced IOs that also use a 0.6V supply when interfacing to LPDDR4X SDRAMs resulting in lower PHY power consumption. The LPDDR4X multiPHY supports LPDDR4X, LPDDR4 and DDR4 SDRAMs up to 4,267 Mbps.

DesignWare DDR Complete Solution Datasheet
DesignWare Enhanced Universal DDR Memory and Protocol Controller IP Datasheet
DesignWare LPDDR4 multiPHY IP Datasheet