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DesignWare LPDDR4 multiPHY / LPDDR4X multiPHY IP
The DesignWare LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR4, LPDDR3, DDR4, DDR3, and/or DDR3L SDRAM interfaces operating at up to 4,267 Mbps. The DesignWare LPDDR4X multiPHY supports LPDDR4X, LPDDR4, and DDR4 SDRAM interfaces operating at up to 4,267 Mbps. With multiple interfaces, these PHYs can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 SDRAMs.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR4 multiPHY is provided as hardened IP components including a 4 slice Address/Command macrocell (ACX4), an 8-bit data macrocell (DBYTE) that includes DM/DBI and data strobes, and a master macrocell (MASTER) that includes the PLL used by the PHY. The macrocells include fully integrated I/Os and are easily assembled into a variety of configurations from a single 16-bit LPDDR4 PHY to a 72-bit DDR4 PHY. An RTL-based PHY utility block (PUB) with firmware-based training capabilities supports the GDSII-based PHY.
The LPDDR4X multiPHY is a similar PHY to the LPDDR4 multiPHY that has been optimized for interfacing to lower power LPDDR4X SDRAMs that use a 0.6V nominal interface. The LPDDR4X multiPHY includes enhanced IOs that also use a 0.6V supply when interfacing to LPDDR4X SDRAMs resulting in lower PHY power consumption. The LPDDR4X multiPHY supports LPDDR4X, LPDDR4 and DDR4 SDRAMs up to 4,267 Mbps.
DesignWare DDR Complete Solution Datasheet DesignWare Enhanced Universal DDR Memory and Protocol Controller IP Datasheet DesignWare IP Prototyping Kits DesignWare IP Prototyping Kits for DDR4/3 and LPDDR4 Controllers DesignWare LPDDR4 multiPHY IP Datasheet IP Accelerated Initiative Brochure
- Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
- Support for data rates up to 4,267 Mbps (process dependent)
- Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
- PHY independent, firmware-based training using an embedded calibration processor
- Optional dual channel architecture for LPDDR3/4/4X modes facilitates two independent channels in less area versus two independent PHYs
- LPDDR4 multiPHY:
- Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
- Maximum data rate is process technology dependent
- Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
- Compatible with JEDEC standard LPDDR3, DDR3 or DDR3L SDRAMs up to 2,133 Mbps
- LPDDR4X multiPHY:
- Compatible with JEDEC standard LPDDR4 or LPDDR4X SDRAMs up to 4,267 Mbps
- DFI 4.0 Version 2 compliant interface to the memory controller
- 1:1, 1:2, and 1:4 clock modes supported
- Optional dual channel DFI for independent 2-channel memories (e.g., LPDDR3/4)
- Flexible channel architecture
- Support for two independent LPDDR4/4X 16-bit channels via one 32-bit PHYs for reduced area and power
- Support for one DDR4/3 interface
- Support for 8-bit, 16-bit, 32-bit and 64-bit wide SDRAMs
- 8-bit and 16-bit DDR3 (LPDDR4 multiPHY only) and DDR4 supported
- 16-bit per channel LPDDR4/4X supported
- 16-bit and 32-bit per channel LPDDR3 supported (LPDDR4 multiPHY only)
- Flexible configuration options:
- LPDDR4/LPDDR4X/LPDDR3: Up to 2 DQ loads, 8 CA loads, and 4 CS loads
- DDR4/DDR3: Up to 4 DQ loads and 4 ranks of CA loading
- Shared AC mode that permits one address and command channel to be time division multiplexed between two independent data channels
- PHY independent, firmware-based training using an embedded calibration processor
- Utilizes specialized hardware acceleration engines
- Automatic periodic retraining through the DFI MASTER interface
- Supports:
- Command Bus Training (VREFCA)
- (LPDDR3, LPDDR4) Command Bus eye training relative to CK
- Write Leveling to compensate for CK-DQS timing skew
- Write Training: DQS to DQ
- Data bus VREFDQ training
- Read training:
- DQ bit deskew training
- DQS to DQ eye centering training using DRAM array
- IO calibration and ODT calibration
| LPDDR4 multiPHY V2 - TSMC16FFC18 for Automotive | STARs | Subscribe |
| LPDDR4X multiPHY - TSMC12FFC18 | STARs | Subscribe |
| LPDDR4X multiPHY - TSMC16FFC18 | STARs | Subscribe |
| LPDDR4X multiPHY - TSMC N7 | STARs | Subscribe |
| LPDDR4 multiPHY - 28FDSOI18 | STARs | Subscribe |
| LPDDR4 multiPHY - TSMC 16FF+GL18 | STARs | Subscribe |
| LPDDR4 multiPHY V2 - SS 10LPP | STARs | Subscribe |
| LPDDR4 multiPHY V2 - SS 14LPP | STARs | Subscribe |
| LPDDR4 multiPHY V2 - TSMC12FFC18 | STARs | Subscribe |
| LPDDR4 multiPHY V2 - TSMC16FFC18 | STARs | Subscribe |
| LPDDR4 multiPHY V2 - TSMC16FF+LL18 | STARs | Subscribe |
| LPDDR4 multiPHY V2 - TSMC28HPC18 | STARs | Subscribe |
| LPDDR4 multiPHY V2 - TSMC28HPC+18 | STARs | Subscribe |
| LPDDR4 multiPHY V2 - UMC 28HPC+18 | STARs | Subscribe |
