The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackage applications requiring high-performance LPDDR5X, LPDDR5, and LPDDR4X SDRAM interfaces operating at up to 8533 Mbps. With flexible configuration options, the LPDDR5X/5/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4X SDRAMs, precisely targeting the specific power, performance, and area (PPA)
requirements of these systems.
Synopsys demonstrates LPDDR5x PHY IP silicon operating at 8533 Mbps, showing wide eyes and clear margins.
Synopsys LPDDR5x/5/4X PHY IP Datasheet
Downloads and Documentation
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Support for data rates up to 8533 Mbps
- Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
- PHY independent, firmware-based training using an embedded calibration processor
- Optional dual channel architecture which facilitates two independent channels in less area versus two independent PHYs
- Support for DFI-based low power modes and lower power sleep and retention modes
- Support for up to 4 trained states/frequencies
- Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
- Built-in anti-aging features to prevent effects of NBTI & HCI