Synopsys LPDDR5X/5/4X PHY IP

The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackage applications requiring high-performance LPDDR5X, LPDDR5, and LPDDR4X SDRAM interfaces operating at up to 8533 Mbps. With flexible configuration options, the LPDDR5X/5/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and/or LPDDR4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

Synopsys LPDDR5x/5/4X PHY IP Datasheet

 

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  • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
  • Support for data rates up to 8533 Mbps
  • Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
  • DFI 5.0 controller interface
  • PHY independent, firmware-based training using an embedded calibration processor
  • Optional dual channel architecture which facilitates two independent channels in less area versus two independent PHYs
  • Support for DFI-based low power modes and lower power sleep and retention modes
  • Support for up to 4 trained states/frequencies
  • Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
  • Built-in anti-aging features to prevent effects of NBTI & HCI
LPDDR5X/5/4X PHY - TSMC N3ESTARs Subscribe
LPDDR5X/5/4X PHY - TSMC N5STARs Subscribe

Description: LPDDR5X/5/4X PHY - TSMC N3E
Name: dwc_lpddr5x_phy_tsmc3eff12
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
  
Description: LPDDR5X/5/4X PHY - TSMC N5
Name: dwc_lpddr5x_phy_tsmc5ff12
Version: 1.00a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dwc_lpddr5x_phy_tsmc5ff12
Product Code: G272-0