DesignWare Interface IP Subsystems

DesignWare Interface IP Subsystems reduce the overall effort and cost of assembling and integrating IP into an SoC, allowing designers to focus their efforts on differentiating their product and speeding time-to-market. The subsystems consist of pre-validated, fully integrated solutions that utilize Synopsys’ IP and tools for the specific SoC application. In addition, Synopsys’ customized IP subsystems provide extra functionality and value over simply integrating a PHY and controller, e.g., common register interface between the PHY and controller, debug logic, and more.

During the IP subsystem engagement, Synopsys experts assist in every stage of SoC design and work directly with the designers to determine design feasibility and performance metrics that are captured in a design specification. Using this specification, Synopsys experts configure, integrate and verify the IP and surrounding logic into a customized IP subsystem. Working with designers to accurately capture design intent at both the block and chip levels, Synopsys experts help to minimize iterations between the architecture and RTL implementation, thereby reducing subsystem integration time.

DesignWare Interface IP Subsystems Datasheet