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DesignWare Interface IP Subsystems
DesignWare Interface IP Subsystems reduce the overall effort and cost of assembling and integrating IP into an SoC, allowing designers to focus their efforts on differentiating their product and speeding time-to-market. The subsystems consist of pre-validated, fully integrated solutions that utilize Synopsys’ IP and tools for the specific SoC application. In addition, Synopsys’ customized IP subsystems provide extra functionality and value over simply integrating a PHY and controller, e.g., common register interface between the PHY and controller, debug logic, and more.
During the IP subsystem engagement, Synopsys experts assist in every stage of SoC design and work directly with the designers to determine design feasibility and performance metrics that are captured in a design specification. Using this specification, Synopsys experts configure, integrate and verify the IP and surrounding logic into a customized IP subsystem. Working with designers to accurately capture design intent at both the block and chip levels, Synopsys experts help to minimize iterations between the architecture and RTL implementation, thereby reducing subsystem integration time.
DesignWare Interface IP Subsystems Datasheet
- Accelerate interface IP subsystem development for complex protocols, such as DDR, PCIe, USB, and Ethernet, as well as multiprotocol subsystems
- Meet critical project schedules by using Synopsys IP protocol and SoC design experts to configure and customize the pre-designed subsystem to the unique SoC requirements.
- Minimize the subsystem integration effort through the use of pre-validated subsystem and verification tests focused on SoC integration
- Reduce overall development costs while enabling designers to focus on their key competencies.
- Provide functionality and value over simple integration of a PHY and controller by including a common register interface between the PHY and controller, debug logic, and more
- Deliverables:
- Pre-configured, pre-validated Synopsys IP for controllers, PHYs and verification (VIP)
- Supplemental subsystem logic for clock, reset, DMA, interrupts, and memory maps
- Power management, debug, and testability logic
- Complete subsystem verification environment that can also be leveraged for SoC verification:
- Scoreboard, checkers and monitors for easy SoC debug
- Comprehensive suite of tests that can be reused at SoC level