DesignWare DDR3/2 SDRAM PHY IP

A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.

DesignWare DDR3/2 PHY Datasheet
 

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• When combined with a DesignWare DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
• Compatible with the DesignWare DDR PHY Compiler
• GUI-based tool used to assemble a customized DDR PHY targeting a specific application
• Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
• Support for DDR3L (1.35V DDR3)
• Many DDR3/2 PHYs also support DDR3U (1.25V DDR3)
• Support for DDR2 and DDR3 DIMMs
• Delivery of product as a hardened Mixed-Signal macrocell components allows precise control of timing critical delay and skew paths
• Low latency
• PHY Utility Block (PUB) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR3/2 PHY
• DFI 2.1 interface to the memory controller
• Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
• Permits operating with DDR3/2 SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
• Support for 1 to 4 memory ranks
• PHY-Controller interface runs in 1:1 or 1:2 mode (ratio of application bus clock to SDRAM clock), simplifying core logic timing constraints
• Includes the PLL and all timing circuits necessary to meet timing specifications
• Write leveling timing circuits to compensate address and control versus data delays
• Write and read bit timing circuits compensate per-bit delay skew of individual data bits within each data byte
• Locally calibrated master and slave timing circuits minimize OCV and ACLV effects, and accommodate voltage or temperature change induced timing drift
• Area optimized I/O
• 6 layers of metal
• 35um I/O pitch for 65nm
• 30um pitch for 40nm
• 25um pitch for 28nm
• Staggered I/O supported
• Supports circuit under pad (CUP) and bond over active (BOA)
• Supports flip chip and wire bond
• I/O retention mode (available with most PHYs)
• Maintains I/O drive state during VDD power down
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
• Accommodates any poly orientation in 28nm processes and below allowing the DDR3/2 PHY to go around a corner if required
• Advanced testability
• At-speed loopback testing on both the address and data channels
• Delay line oscillator test mode
• MUX-scan ATPG
• Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments

DDR3/2 PHY - Area Reduced SS 45LP25	STARs	Subscribe
DDR3/2 PHY - CHRT 65G25 V2	STARs	Subscribe
DDR3/2 PHY - GF 28HPP18	STARs	Subscribe
DDR3/2 PHY - GF 28SLP18	STARs	Subscribe
DDR3/2 PHY - GF 40LP25	STARs	Subscribe
DDR3/2 PHY - SMIC 40LL25	STARs	Subscribe
DDR3/2 PHY - SS 32LP18	STARs	Subscribe
DDR3/2 PHY - SS 45LP25	STARs	Subscribe
DDR3/2 PHY - ST 28FDSOI18	STARs	Subscribe
DDR3/2 PHY - ST 28LP18	STARs	Subscribe
DDR3/2 PHY - TSMC 28HP18	STARs	Subscribe
DDR3/2 PHY - TSMC 28HPC18	STARs	Subscribe
DDR3/2 PHY - TSMC 28HPM18	STARs	Subscribe
DDR3/2 PHY - TSMC 40G18	STARs	Subscribe
DDR3/2 PHY - TSMC 40LP25	STARs	Subscribe
DDR3/2 PHY - TSMC 55GP25	STARs	Subscribe
DDR3/2 PHY - TSMC 65GP25	STARs	Subscribe
DDR3/2 PHY - UMC 40LP25	STARs	Subscribe
DDR3/2 PHY - UMC 55SP25	STARs	Subscribe
DDR3/2 PHY - UMC 65SP25	STARs	Subscribe

Description	DDR3/2 PHY - Area Reduced SS 45LP25
Name	dwc_ddr3_ddr2_phy_ar_ss45lp25
Version	1.40a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, …
Download	DDR3-2-PHY_SS_AR_45LP
Product Code	A549-0
Description	DDR3/2 PHY - CHRT 65G25 V2
Name	dwc_ddr3_ddr2_phy_chrt65g25_v2
Version	2.60a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.xx DesignWare Cores DDR3/2 SDRAM PHY Databook Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_CP_65G25-V2
Product Code	7604-0
Description	DDR3/2 PHY - GF 28HPP18
Name	dwc_ddr3_ddr2_phy_gf28hpp18
Version	1.20b
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.16 DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY
Download	DDR3-2-PHY_GF_28HPP
Product Code	A547-0
Description	DDR3/2 PHY - GF 28SLP18
Name	dwc_ddr3_ddr2_phy_gf28slp18
Version	1.50a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_GF_28SLP18
Product Code	4789-0
Description	DDR3/2 PHY - GF 40LP25
Name	dwc_ddr3_ddr2_phy_gf40lp25
Version	1.51a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_GF_40LP25
Product Code	4788-0
Description	DDR3/2 PHY - SMIC 40LL25
Name	dwc_ddr3_ddr2_phy_smic40ll25
Version	1.40a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_SMIC_40LL25
Product Code	9977-0
Description	DDR3/2 PHY - SS 32LP18
Name	dwc_ddr3_ddr2_phy_ss32lp18
Version	1.50a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, …
Download	DDR3-2-PHY_SS_32LP
Product Code	A550-0
Description	DDR3/2 PHY - SS 45LP25
Name	dwc_ddr3_ddr2_phy_ss45lp25
Version	2.20a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, …
Download	DDR3-2-PHY_SS_45LP
Product Code	A548-0
Description	DDR3/2 PHY - ST 28FDSOI18
Name	dwc_ddr3_ddr2_phy_st28fdsoi18
Version	1.20a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Datasheet DesignWare DDR3/2 PHY Datasheet Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_ST_28FDSOI18
Product Code	A796-0
Description	DDR3/2 PHY - ST 28LP18
Name	dwc_ddr3_ddr2_phy_st28lp18
Version	1.30a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR Complete Solution Datasheet DesignWare DDR3/2 PHY Datasheet Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_ST_28LP18
Product Code	4981-0
Description	DDR3/2 PHY - TSMC 28HP18
Name	dwc_ddr3_ddr2_phy_tsmc28hp18
Version	1.60a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.xx DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_28HP18
Product Code	4753-0
Description	DDR3/2 PHY - TSMC 28HPC18
Name	dwc_ddr3_ddr2_phy_tsmc28hpc18
Version	2.21a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Datasheet DesignWare DDR Complete Solution Datasheet Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_28HPC18
Product Code	B135-0
Description	DDR3/2 PHY - TSMC 28HPM18
Name	dwc_ddr3_ddr2_phy_tsmc28hpm18
Version	2.21a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_28HPM18
Product Code	4787-0
Description	DDR3/2 PHY - TSMC 40G18
Name	dwc_ddr3_ddr2_phy_tsmc40g18
Version	2.90a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.16 DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_40G18
Product Code	7607-0
Description	DDR3/2 PHY - TSMC 40LP25
Name	dwc_ddr3_ddr2_phy_tsmc40lp25
Version	3.10a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_40LP25
Product Code	6929-0
Description	DDR3/2 PHY - TSMC 55GP25
Name	dwc_ddr3_ddr2_phy_tsmc55gp25
Version	2.50a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.17 DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_55GP25
Product Code	6930-0
Description	DDR3/2 PHY - TSMC 65GP25
Name	dwc_ddr3_ddr2_phy_tsmc65gp25
Version	2.70a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.17 DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_TSMC_65GP25
Product Code	4933-0
Description	DDR3/2 PHY - UMC 40LP25
Name	dwc_ddr3_ddr2_phy_umc40lp25
Version	1.10a
STARs	Open and/or Closed STARs
myDesignWare	Subscribe for Notifications
Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.18 DesignWare Cores DDR3/2 SDRAM PHY Datasheet DesignWare DDR Complete Solution Datasheet Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY Release Notes
Download	DDR3-2-PHY_UMC_40LP25
Product Code	9978-0
Description	DDR3/2 PHY - UMC 55SP25
Name	dwc_ddr3_ddr2_phy_umc55sp25
Version	2.30a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.xx DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY
Download	DDR3-2-PHY_UMC_55SP25
Product Code	7564-0
Description	DDR3/2 PHY - UMC 65SP25
Name	dwc_ddr3_ddr2_phy_umc65sp25
Version	2.40a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Application Notes BIST Loopback Mode Guidelines for Implementing Signaling Environments for DDRn Interfaces: PCB, Package, … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Databook, 3.17 DesignWare Cores DDR3/2 SDRAM PHY Datasheets DesignWare DDR3/2 PHY Datasheet DesignWare IP for Data Centers Brochure Implementation Guide DesignWare Cores DDR3/2 SDRAM PHY Installation Guide DesignWare Cores DDR3/2 SDRAM PHY Release Notes DesignWare Cores DDR3/2 SDRAM PHY
Download	DDR3-2-PHY_UMC_65SP25
Product Code	7608-0