DesignWare LPDDR5/4/4X PHY IP

The DesignWare LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:

Single-ended Command/Address (C/A) and Data (DQ) signals
Differential signals (clock, data strobe, and WCK signals)
CMOS logic-level based C/A signals

The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the DesignWare LPDDR5/4/4X Controller for a complete DDR interface solution.

DesignWare LPDDR5/4/4X PHY IP Datasheet

Highlights

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Downloads and Documentation

Supports JEDEC standard LPDDR5, LPDDR4 and LPDDR4X SDRAMs
Support for data rates up to 6400Mbps
Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
DFI 5.0 controller interface
PHY independent, firmware-based training using an embedded calibration processor
Optional dual channel architecture for LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs
Support for DFI-based low power modes and lower power sleep and retention modes
Support for up to 15 trained states/frequencies
Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
Built-in anti-aging features to prevent effects of NBTI & HCI

LPDDR5/4/4X PHY - TSMC 16FFC	STARs	Subscribe
LPDDR5/4/4X PHY - TSMC N7	STARs	Subscribe

Description:	LPDDR5/4/4X PHY - TSMC 16FFC
Name:	dwc_lpddr54_phy_tsmc16ffc
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information

Description:	LPDDR5/4/4X PHY - TSMC N7
Name:	dwc_lpddr54_phy_tsmc7ff18
Version:	1.20a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks DesignWare Cores LPDDR5/4/4x PHY Databook DesignWare Cores LPDDR5/4/4x PHY Utility Block Databook (PUB) Implementation Guide DesignWare Cores LPDDR5/4/4x PHY Implementation Guide Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes
Download:	LPDDR5-4-m-PHY_TSMC_N7
Product Code:	D221-0