DesignWare LPDDR5/4/4X PHY IP

The DesignWare LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:

Single-ended Command/Address (C/A) and Data (DQ) signals
Differential signals (clock, data strobe, and WCK signals)
CMOS logic-level based C/A signals

The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the DesignWare LPDDR5/4/4X Controller for a complete DDR interface solution.

DesignWare LPDDR5/4/4X PHY IP Datasheet

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Downloads and Documentation

Supports JEDEC standard LPDDR5, LPDDR4 and LPDDR4X SDRAMs
Support for data rates up to 6400Mbps
Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
DFI 5.0 controller interface
PHY independent, firmware-based training using an embedded calibration processor
Optional dual channel architecture for LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs
Support for DFI-based low power modes and lower power sleep and retention modes
Support for up to 15 trained states/frequencies
Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
Built-in anti-aging features to prevent effects of NBTI & HCI

LPDDR5/4/4X PHY - TSMC N7 for Automotive	STARs	Subscribe
LPDDR5/4/4X PHY - TSMC 12FFC	STARs	Subscribe
LPDDR5/4/4X PHY - TSMC 16FFC	STARs	Subscribe
LPDDR5/4/4X PHY - TSMC N5	STARs	Subscribe
LPDDR5/4/4X PHY - TSMC N6	STARs	Subscribe
LPDDR5/4/4X PHY - TSMC N7	STARs	Subscribe

Description:	LPDDR5/4/4X PHY - TSMC 12FFC
Name:	dwc_lpddr54_phy_tsmc12ffc
Version:	2.20a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF ) DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application … ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:1.03b) ( PDF \| HTML ) DesignWare Cores LPDDR54 PHY HSPICE Model for TSMC12FFC18 (Version: 2.00a-ew) ( PDF ) Databooks DesignWare Cores LPDDR5/4/4X PHY Databook for TSMC12FFC18 (2.20a) ( PDF \| HTML ) DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.05b) ( PDF \| HTML ) Implementation Guide DesignWare Cores LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.40a) ( PDF \| HTML ) Release Notes DesignWare Cores LPDDR5/4/4X PHY Release Notes (PHY Version 2.20a) ( TXT )
Download:	dwc_lpddr54_phy_tsmc12ffc18
Product Code:	D774-0

Description:	LPDDR5/4/4X PHY - TSMC 16FFC
Name:	dwc_lpddr54_phy_tsmc16ffc
Version:	2.10a-ew
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF ) DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application … ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF ) DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:1.03b) ( PDF \| HTML ) DesignWare Cores LPDDR54 PHY HSPICE Model for TSMC16FFC18 (Version: 2.10a-ew) ( PDF ) Databooks DesignWare Cores LPDDR5/4/4X PHY Databook for TSMC16FFC1 (PHY Version: 2.10a-ew) ( HTML \| PDF ) DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.03b) ( PDF \| HTML ) Implementation Guide DesignWare Cores LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.40a) ( PDF \| HTML ) Release Notes DesignWare Cores LPDDR5/4/4X PHY Release Notes (PHY Version: 2.10a-ew) ( TXT )
Download:	dwc_lpddr54_phy_tsmc16ffc18
Product Code:	D773-0

Description:	LPDDR5/4/4X PHY - TSMC N5
Name:	dwc_lpddr54_phy_tsmc5ff12
Version:	2.00a
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application … ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Loopback Features Application Note ( PDF ) DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF ) DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:1.05b) ( PDF \| HTML ) DesignWare Cores LPDDR54 PHY HSPICE Model for TSMC5FFP12 ( PDF ) DesignWare Cores LPDDR54 PHY Training Firmware Application Note (FW Version: … ( PDF ) Databooks DesignWare Cores LPDDR5/4/4x PHY Databook for TSMC5FF12 (PHY Version: 2.00a) ( PDF \| HTML ) DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.05b) ( PDF \| HTML ) Implementation Guide DesignWare Cores LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.40a) ( PDF \| HTML ) Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes for TSMC5FFP12 (PHY Version: 2.00a) ( PDF )
Download:	dwc_lpddr54_phy_tsmc5ff12
Product Code:	E377-0

Description:	LPDDR5/4/4X PHY - TSMC N6
Name:	dwc_lpddr54_phy_tsmc6ff18
Version:	1.10a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF ) DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application … ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF ) DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:1.05b) ( PDF \| HTML ) DesignWare Cores LPDDR54 PHY Diagnostics Firmware Application Note (FW Version: … ( PDF ) DesignWare Cores LPDDR54 PHY Firmware ATE Application Note (FW Version: … ( PDF ) DesignWare Cores LPDDR54 PHY Training Firmware Application Note (FW Version: … ( PDF ) Databooks DesignWare Cores LPDDR5/4/4X PHY Databook for TSMC6FF (PHY Version: 1.10a) ( PDF \| HTML ) DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.05b) ( PDF \| HTML ) Implementation Guide DesignWare Cores LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.40a) ( PDF \| HTML ) Release Notes DesignWare Cores LPDDR5/4/4X PHY Release Notes (PHY Version: 1.10a) ( TXT )
Download:	dwc_lpddr54_phy_tsmc6ff18
Product Code:	E562-0

Description:	LPDDR5/4/4X PHY - TSMC N7
Name:	dwc_lpddr54_phy_tsmc7ff18
Version:	3.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application … ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores LPDDR5/4/4X PHY PHYInit Software Overview Application Note ( PDF ) DesignWare Cores LPDDR5/4/4X PHY coreKit User Guide (coreKit Version:1.05b) ( PDF \| HTML ) DesignWare Cores LPDDR54 PHY Diagnostics Firmware Application Note (FW Version: … ( PDF ) DesignWare Cores LPDDR54 PHY Firmware ATE Application Note (FW Version: … ( PDF ) DesignWare Cores LPDDR54 PHY Training Firmware Application Note (FW Version: … ( PDF ) Databooks DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.05b) ( PDF \| HTML ) DesignWare Cores LPDDR5/4/4x PHY Databook for TSMC7FF18 (PHY Version: 3.00a) ( PDF \| HTML ) Implementation Guide DesignWare Cores LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.40a) ( PDF \| HTML ) Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes (PHY Version: 3.00a) ( TXT )
Download:	dwc_lpddr54_phy_tsmc7ff18
Product Code:	D221-0

Description:	LPDDR5/4/4X PHY - TSMC N7 for Automotive
Name:	dwc_ap_lpddr54_phy_tsmc7ff18
Version:	2.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Unsubscribe
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores LPDDR5/4 PHY OCC Implementation Using Internal PLL Application … ( PDF ) DesignWare Cores LPDDR5/4/4X PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) Databooks DesignWare Cores LPDDR5/4/4x PHY Databook for Automotive Grade 2 (AP) TSMC7FF18 … ( PDF \| HTML ) DesignWare Cores LPDDR5/4/4X PHY Utility Block Databook (PUB Version: 1.02a_patch3) ( PDF \| HTML ) Implementation Guide DesignWare Cores LPDDR5/4/4X PHY Implementation Guide (Doc. Version 2.40a) ( PDF \| HTML ) Reference Manual DesignWare Cores LPDDR5/4/4x PHY Reliability Report for Automotive Grade 2 (AP) … ( PDF ) Release Notes DesignWare Cores LPDDR5/4/4x PHY Release Notes for Automotive Grade 2 (AP) … ( TXT )
Download:	dwc_ap_lpddr54_phy_tsmc7ff18
Product Code:	D771-0