The DesignWare LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals: DesignWare LPDDR5/4/4X PHY IP Datasheet
Description: | LPDDR5/4/4X PHY - TSMC 16FFC |
Name: | dwc_lpddr54_phy_tsmc16ffc |
STARs: | Open and/or Closed STARs |
myDesignWare: | Subscribe for Notifications |
Product Type: | DesignWare Cores |
Documentation: | Contact Us for More Information |
Description: | LPDDR5/4/4X PHY - TSMC N7 |
Name: | dwc_lpddr54_phy_tsmc7ff18 |
Version: | 1.20a |
STARs: | Open and/or Closed STARs |
myDesignWare: | Subscribe for Notifications |
Product Type: | DesignWare Cores |
Documentation: | |
Download: | LPDDR5-4-m-PHY_TSMC_N7 |
Product Code: | D221-0 |