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Synopsys LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR6, LPDDR5X and/or LPDDR5 SDRAMs. The controller connects to the Synopsys LPDDR6/5X/5 PHY or other LPDDR6/5X/5 PHYs via the DFI 5.2 interface to create a complete memory interface solution.
The Synopsys LPDDR6/5X/5 Controller IP includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The LPDDR6/5X/5 Controller IP block includes advanced command scheduler, memory protocol handler, enhanced RAS capabilities with high flexibility to use Metadata, Advanced ECC and Link ECC. It also provides the option for a single or dual channel configuration topology for suitable applications.
The Synopsys LPDDR6/5X/5 Controller IP seamlessly integrates the Synopsys Inline Memory Encryption (IME) Security IP Module to provide confidentiality of data in-use or stored in off-chip memory. Synopsys Secure LPDDR6/5/5X Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the Synopsys secure memory controllers is as low as 2 clock cycles.
The Synopsys LPDDR6/5X/5 Controller IP in combination with LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications targeting the specific power, performance, and area (PPA) requirements of these systems aiming to address traditional mobile environments, consumer products.
Highlights & Key Features
- Supports JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
- Support for data rates up to 14.4 Gbps for LPDDR6, 10.67 Gbps for LPDDR5X, and 6.4 Gbps for LPDDR5
- Multiport Arm® AMBA® interface AXI™4 with managed QoS or single-port host interface to the DDR controller
- DFI 5.2 compliant interface to Synopsys LPDDR6/5X/5 PHY
- Best-in-class performance with unique features such as QoS-based for dynamic scheduling and out-of-order commands execution for maximum SDRAM efficiency
- High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes with latency as low as 5 clock cycles
- Supports up to 4 memory ranks
- UVM testbench with embedded assertions and options to incorporate an LPDDR6/5X/5 PHY into a verification environment
- Fully integrated with Synopsys Inline Memory Encryption (IME) to provide data confidentiality and lowest latency solution
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