Synopsys Enhanced Universal DDR Memory Controller (uMCTL2)

The Synopsys Enhanced Universal Memory Controller (uMCTL2) is fully configurable controller that allows designers to generate a DDR controller that is optimized for latency, bandwidth, and area. The configurable uMCTL2 allows for the generation of DDR controllers that meet or exceed the requirements of designs ranging from high-performance networking to low-power, cost-sensitive mobile products. The uMCTL2 DDR supports the JEDEC standard DDR4, DDR3, DDR2, LPDDR4, LPDDR3, LPDDR2, and LPDDR/mobile DDR SDRAMs.

The uMCTL2 delivers maximum bandwidth with low latency. This advanced memory controller accepts memory access requests from between 1 and 16 application-side host ports. Application-side interfaces can be connected to the uMCTL2 either through standard AMBA (AXI4, AXI or AHB) bus interfaces for one or multiple ports, or via Synopsys’ custom-defined host-interface H-IF for single-port ultra low latency configurations.

The uMCTL2’s low-power features make it useful in power-sensitive designs, and uMCTL2’s reliability, availability, and serviceability (RAS) features meet the needs of the most demanding enterprise systems.

The uMCTL2 offers many features to maximize performance: high-priority bypass that reduces latency, configurable look-ahead of up to 64 read and 64 write commands, dual address queues per port to reduce head-of-line blocking, quality of service (QoS) to improve system performance, variable priority commands, a read reorder buffer (RRB) to allow out-of-order execution with in-order responses, and more.

The uMCTL2 supports powerful features to optimize DDR memory efficiency for applications while managing quality of service for individual transaction streams.