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The Synopsys DDR2/DDR SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/DDR physical layer (PHY) in a DDR2 or DDR memory subsystem. The MCTL IP is a full-featured controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.
Highlights & Key Features
- Provides a complete, single vendor DDR2/DDR SDRAM interface solution, when combined with the Synopsys DDR2/DDR PHY IP
- Supports JEDEC-standard DDR2 and DDR protocols (JESD79-2 and JESD79, respectively)
- Supports data rates of up to 1066 Mbps (533 MHz)
- Includes a configurable multi-port arbiter with up to 32 host ports using Host Memory Interface (HMI) or AMBA 3 AXI
- Programmable ultra-high priority port (port 0), typically a CPU port
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