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The Synopsys DDR2/3-Lite SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite physical layer (PHY) in a DDR3 or DDR2 memory subsystem. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.
Highlights & Key Features
- Provides a complete, single vendor DDR3/2 SDRAM interface IP solution, when combined with the Synopsys DDR2/3-Lite PHY IP
- Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
- Supports data rates of up to 1066Mbps (533 MHz)
- Includes a configurable multi-port arbiter with up to 32 host ports using Host Memory Interface (HMI), AMBA AHB or AMBA 3 AXI
- Programmable ultra-high priority port (port 0), typically a CPU port
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