2024-10-02 07:57:38
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 8400 Mbps. The synopsys DDR5/4 PHY is ideal for systems that require high-speed, high-performance, and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB)that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
Synopsys DDR5/4 PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 8400 Mbps
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/ frequencies with <3μs switching time
- I/O receiver decision feedback equalization
- VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
- DFI 5.0-compliant controller interface
- Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution
Description: |
DDR5 PHY - SS SF4X |
Name: |
dwc_ddr5_phy_sssf4x |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform Application Note (Version 2022.11_1) ( PDF | HTML )
DesignWare Cores DDR5 PHY Boundary Scan Implementation Application Note (Version: 1.10a) ( PDF | HTML )
DesignWare Cores DDR5 PHY Initialization (PHYInit) Software Overview Application Note (Version 0.90a) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY ATE Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY CTB and Verification Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Diagnostics Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Interconnect Signal and Power Integrity Guidelines Application Note (Version 0.40a) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Training Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY coreKit User Guide Application Note (Version: 1.21a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5 PHY Utility Block (PUB) Databook (PUB Version: 1.21a_d2) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Databook for Samsung SF4X (PHY Version: 1.00a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP DDR5 PHY Implementation Guide (Version 1.40a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5 PHY Databook for Samsung SF4X Release Notes (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_ddr5_phy_sssf4x |
Product Code: |
I123-0 |
Description: |
DDR5 PHY - TSMC N3E |
Name: |
dwc_ddr5_phy_tsmc3eff12 |
Version: |
1.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform Application Note (Version 2022.11_1) ( PDF | HTML )
DesignWare Cores DDR5 PHY ATE Firmware Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY Boundary Scan Implementation Application Note (Version: 1.10a) ( PDF | HTML )
DesignWare Cores DDR5 PHY CTB and Verification Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY Diagnostics Firmware Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY IBIS Model Application Note (Version 1.10a) ( PDF | HTML )
DesignWare Cores DDR5 PHY Initialization (PHYInit) Software Overview Application Note (Version 0.90a) ( PDF | HTML )
DesignWare Cores DDR5 PHY Training Firmware Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY coreKit User Guide Application Note (Version: 1.10a) ( PDF | HTML )
DesignWare Cores DDRPHY Backdoor Support Application Note (Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Interconnect Signal and Power Integrity Guidelines Application Note (Version 0.40a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5 PHY Databook for TSMC3EFF12 (PHY Version: 1.10a_d1) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Utility Block (PUB) Databook (PUB Version: 1.20a_d3) ( PDF | HTML )
Implementation Guide Synopsys PHY IP DDR5 PHY Implementation Guide (Version 1.40a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5 PHY Databook for TSMC3EFF12 Release Notes (PHY Version: 1.10a) ( TEXT )
|
Download: |
dwc_ddr5_phy_tsmc3eff12 |
Product Code: |
G271-0 |
Description: |
DDR5 PHY - TSMC N3P |
Name: |
dwc_ddr5_phy_tsmc3pff12 |
Version: |
1.00a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform Application Note (Version 2022.11_1) ( PDF | HTML )
DesignWare Cores DDR5 PHY Boundary Scan Implementation Application Note (Version: 1.10a) ( PDF | HTML )
DesignWare Cores DDR5 PHY Initialization (PHYInit) Software Overview Application Note (Version 0.90a) ( PDF | HTML )
DesignWare Cores DDRPHY Backdoor Support Application Note (Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY ATE Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY CTB and Verification Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Diagnostics Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Interconnect Signal and Power Integrity Guidelines Application Note (Version 0.40a) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Training Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY coreKit User Guide Application Note (Version: 1.21a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5 PHY Utility Block (PUB) Databook (PUB Version: 1.21a_d2) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Databook for TSMC3PFF12 (PHY Version: 1.00a_d1) ( PDF | HTML )
Implementation Guide Synopsys PHY IP DDR5 PHY Implementation Guide (Version 1.40a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5 PHY Databook for TSMC3PFF12 Release Notes (PHY Version: 1.00a) ( TEXT )
|
Download: |
dwc_ddr5_phy_tsmc3pff12 |
Product Code: |
G271-0 |
Description: |
DDR5 PHY - TSMC N5 |
Name: |
dwc_ddr5_phy_tsmc5ff12 |
Version: |
1.20a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform Application Note (Version 2022.11_1) ( PDF | HTML )
DesignWare Cores DDR5 PHY ATE Firmware Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY Boundary Scan Implementation Application Note (Version: 1.10a) ( PDF | HTML )
DesignWare Cores DDR5 PHY CTB and Verification Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY Diagnostics Firmware Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY IBIS Model Application Note (Version 1.10a) ( PDF | HTML )
DesignWare Cores DDR5 PHY Initialization (PHYInit) Software Overview Application Note (Version 0.90a) ( PDF | HTML )
DesignWare Cores DDR5 PHY Training Firmware Application Note (FW Version: A-2023.11) ( PDF | HTML )
DesignWare Cores DDR5 PHY coreKit User Guide Application Note (Version: 1.20a) ( PDF | HTML )
DesignWare Cores DDRPHY Backdoor Support Application Note (Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Diagnostics Firmware Application Note (FW Version: A-2024.06) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Interconnect Signal and Power Integrity Guidelines Application Note (Version 0.40a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5 PHY Utility Block (PUB) Databook (PUB Version: 1.21a_d2) ( PDF | HTML )
Synopsys PHY IP DDR5 PHY Databook for TSMC5FF12 (PHY Version: 1.20a_d1) ( PDF | HTML )
Implementation Guide Synopsys PHY IP DDR5 PHY Implementation Guide (Version 1.40a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5 PHY Databook for TSMC5FF12 Release Notes (PHY Version: 1.20a) ( TEXT )
|
Download: |
dwc_ddr5_phy_tsmc5ff12 |
Product Code: |
G270-0 |
Description: |
DDR5/4 PHY - GF 12LP+ |
Name: |
dwc_ddr54_phy_gf12lpp18 |
Version: |
1.10a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY CTB and Verification Application Note (CTB Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Training Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY coreKit User Guide (coreKit Version: 3.70a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5/4 PHY Databook for GF12LPP18 (PHY Version: 1.10a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Utility Block Databook (PUB Version: 3.70a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5/4 PHY Release Notes for GF12 LPP18 (PHY Version 1.10a) ( TEXT )
|
Download: |
dwc_ddr54_phy_gf12lpp18 |
Product Code: |
F757-0 |
Description: |
DDR5/4 PHY - SS 10LPP |
Name: |
dwc_ddr54_phy_ss10lpp |
Version: |
1.21a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.20a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY Firmware ATE Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY Firmware Training Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for SS10LPP (PHY Version: 1.21a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes DesignWare Cores DDR5/4 PHY Release Notes (PHY Version 1.21a) ( TEXT )
|
Download: |
dwc_ddr54_phy_sams10lpp18 |
Description: |
DDR5/4 PHY - SS 7LPP |
Name: |
dwc_ddr54_phy_ss7lpp |
Version: |
1.11b |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.20a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY Firmware ATE Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY Firmware Training Application Note (FW Version: A/B/C/D/E-2020.08) ( PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR Interfaces Application Note ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for SAMS7LPP18 (PHY Version:1.11b) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 PHY Release Notes (PHY Version:1.11b) ( TEXT )
|
Download: |
dwc_ddr54_phy_sams7lpp18 |
Description: |
DDR5/4 PHY - TSMC 12FFC |
Name: |
dwc_ddr54_phy_tsmc12ffc |
Version: |
1.32a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY CTB and Verification Application Note (CTB Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Training Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY coreKit User Guide (coreKit Version: 3.70a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5/4 PHY Databook for TSMC12FFC18 (PHY Version: 1.32a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Utility Block Databook (PUB Version: 3.70a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5/4 PHY Databook for TSMC12FFC18 Release Notes (PHY Version: 1.32a) ( TEXT )
|
Download: |
dwc_ddr54_phy_tsmc12ffc |
Product Code: |
D779-0 |
Description: |
DDR5/4 PHY - TSMC 16FFC |
Name: |
dwc_ddr54_phy_tsmc16ffc |
Version: |
1.31a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY CTB and Verification Application Note (CTB Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Training Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY coreKit User Guide (coreKit Version: 3.70a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5/4 PHY Databook for TSMC16FFC18 (PHY Version: 1.31a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Utility Block Databook (PUB Version: 3.70a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR5/4 PHY Databook for TSMC16FFC18 Release Notes (PHY Version: 1.31a) ( TEXT )
|
Download: |
dwc_ddr54_phy_tsmc16ffc |
Product Code: |
D778-0 |
Description: |
DDR5/4 PHY V2 - TSMC N5 |
Name: |
dwc_ddr54_phy_v2_tsmc5ff12 |
Version: |
1.40a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform Application Note (Version 2022.11) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY CTB and Verification Application Note (CTB Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Training Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 IBIS Model Application Note (Version 1.54a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 coreKit User Guide (coreKit Version: 4.40a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5/4 PHY V2 Databook for TSMC5FF12 (PHY Version: 1.40a_d1) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 Utility Block Databook (PUB Version: 4.40a) ( PDF | HTML )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR54 V2 PHY Release Notes for TSMC5FF12 (PHY Version: 1.40a) ( TEXT )
|
Download: |
dwc_ddr54_phy_v2_tsmc5ff12 |
Product Code: |
F451-0 |
Description: |
DDR5/4 PHY V2 - TSMC N6 |
Name: |
dwc_ddr54_phy_v2_tsmc6ff18 |
Version: |
1.60a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY CTB and Verification Application Note (CTB Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Training Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 IBIS Model Application Note (Version 1.54a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 coreKit User Guide (coreKit Version: 4.40a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5/4 PHY V2 Databook for TSMC6FF18 (PHY Version: 1.60a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 Utility Block Databook (PUB Version: 4.40a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR54 PHY V2 Release Notes for TSMC6FF18 (PHY Version:1.60a) ( TEXT )
|
Download: |
dwc_ddr54_phy_v2_tsmc6ff18 |
Product Code: |
F752-0 |
Description: |
DDR5/4 PHY V2 - TSMC N7 |
Name: |
dwc_ddr54_phy_v2_tsmc7ff18 |
Version: |
2.70a |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform Application Note (Version 2022.11) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Boundary Scan Implementation Application Note (Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note(Doc. Version: 1.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY CTB and Verification Application Note (CTB Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines (Version: 2.30a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY Training Firmware Application Note (FW Version: F-2024.07) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 IBIS Model Application Note (Version 1.54a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 coreKit User Guide (coreKit Version: 4.40a) ( PDF | HTML )
Databooks Synopsys PHY IP DDR5/4 PHY V2 Databook for TSMC7FF18 (PHY Version: 2.70a) ( PDF | HTML )
Synopsys PHY IP DDR5/4 PHY V2 Utility Block Databook (PUB Version: 4.40a) ( PDF | HTML )
Datasheet Synopsys DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide Synopsys PHY IP DDR5/4 PHY and DDR5/4 PHY V2 Implementation Guide (Version: 2.60a) ( PDF | HTML )
Release Notes Synopsys PHY IP DDR54 PHY V2 Release Notes for TSMC7FF18 (PHY Version: 2.70a) ( TEXT )
|
Download: |
dwc_ddr54_phy_v2_tsmc7ff18 |
Product Code: |
F450-0 |