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DesignWare DDR5/4 PHY IP
The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 6400 Mbps. The DesignWare DDR5/4 PHY is ideal for systems that require high-speed, high-performance, and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB)that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
DesignWare DDR5/4 PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 6400 Mbps
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/ frequencies with <3μs switching time
- I/O receiver decision feedback equalization
- VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
- DFI 5.0-compliant controller interface
- Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution
| Description: | DDR5/4 PHY - SS 10LPP |
| Name: | dwc_ddr54_phy_ss10lpp |
| Version: | 1.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note ( PDF ) DesignWare Cores DDR54 PHY PHYInit Software Overview Application Note ( PDF ) Databooks DesignWare Cores DDR5/4 PHY Databook for SS10LPP (PHY Version: 1.20a) ( PDF ) DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( PDF ) Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 0.35a) ( PDF ) Release Notes DesignWare Cores DDR5/4 PHY Release Notes (PHY Version 1.20a) ( TXT ) |
| Download: | dwc_ddr54_phy_sams10lpp18 |
| Product Code: | D776-0 |
| Description: | DDR5/4 PHY - SS 7LPP |
| Name: | dwc_ddr54_phy_ss7lpp |
| Version: | 1.10a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note ( PDF ) DesignWare Cores DDR54 PHY PHYInit Software Overview Application Note ( PDF ) Databooks DesignWare Cores DDR5/4 PHY Databook for SAMS7LPP18 (PHY Version:1.10a) ( PDF ) DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( PDF ) Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 0.35a) ( PDF ) Release Notes DesignWare Cores DDR54 PHY Release Notes (PHY Version:1.10a) ( TXT ) |
| Download: | dwc_ddr54_phy_sams7lpp18 |
| Product Code: | D777-0 |
| Description: | DDR5/4 PHY - TSMC 12FFC |
| Name: | dwc_ddr54_phy_tsmc12ffc |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores DDR5/4 PHY Firmware Training Application Note ( PDF ) DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note ( PDF ) DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.00a) ( PDF ) DesignWare Cores DDR54 PHY HSPICE Model for TSMC12FFC18 ( PDF ) DesignWare Cores DDR54 PHY PHYInit Software Overview Application Note ( PDF ) DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: … ( PDF ) Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC12FFC18 (PHY Version: 1.00a) ( PDF ) DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version: 3.00a) ( PDF ) DesignWare Cores DDR5/4 PHY Databook ( HTML ) Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.20a) ( PDF ) Release Notes DesignWare Cores DDR5/4 PHY Databook for TSMC12FFC18 Release Notes (PHY … ( TXT ) |
| Download: | DDR5-PHY_TSMC_12FFC |
| Product Code: | D779-0 |
| Description: | DDR5/4 PHY - TSMC 16FFC |
| Name: | dwc_ddr54_phy_tsmc16ffc |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores DDR5/4 PHY Firmware Training Application Note ( PDF ) DesignWare Cores DDR5/4 PHY HSPICE Model for TSMC16ffc18 ( PDF ) DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note ( PDF ) DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.00a) ( PDF ) DesignWare Cores DDR54 PHY PHYInit Software Overview Application Note ( PDF ) DesignWare Cores DDRn PHY Diagnostics Firmware Application Note (FW Version: … ( PDF ) Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC16FFC18 (PHY Version: 1.00a) ( PDF ) DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version: 3.00a) ( PDF ) Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.20a) ( PDF ) Release Notes DesignWare Cores DDR5/4 PHY Databook for TSMC16FFC18 Release Notes (PHY … ( TXT ) |
| Download: | DDR5-PHY_TSMC_16FFC |
| Product Code: | D778-0 |
| Description: | DDR5/4 PHY - TSMC N5 |
| Name: | dwc_ddr54_phy_tsmc5ff12 |
| Version: | 1.10a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores DDR5/4 PHY Firmware Training Application Note ( PDF ) DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note ( PDF ) DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.00a) ( PDF ) DesignWare Cores DDR54 PHY HSPICE Model for tsmc5ffp12 ( PDF ) DesignWare Cores DDR54 PHY PHYInit Software Overview Application Note ( PDF ) Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC5FFP12 (1.10a) ( PDF ) DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB) Databook (3.10b) ( HTML | PDF ) Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.20a) ( PDF ) Release Notes DesignWare Cores DDR54 PHY Release Notes for TSMC5FFP12 (PHY Version:1.10a) ( TXT ) |
| Download: | dwc_ddr54_phy_tsmc5ffp12 |
| Product Code: | E378-0 |
| Description: | DDR5/4 PHY - TSMC N7 |
| Name: | dwc_ddr54_phy_tsmc7ff18 |
| Version: | 1.30a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Unsubscribe |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF ) DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application Note ( PDF ) DesignWare Cores DDR54 PHY PHYInit Software Overview Application Note ( PDF ) Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC7FF18 (PHY Version: 1.30a) ( PDF ) DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( PDF ) Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.20a) ( PDF ) Release Notes DesignWare Cores DDR54 PHY Release Notes (PHY Version: 1.30a) ( TXT ) |
| Download: | dwc_ddr54_phy_tsmc7ff18 |
| Product Code: | D220-0 |