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DesignWare DDR5/4 PHY IP
The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 4800 Mbps. The DesignWare DDR5/4 PHY is ideal for systems that require high-speed, high-performance, and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB)that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
DesignWare DDR5/4 PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 4800 Mbps
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/ frequencies with <3μs switching time
- I/O receiver decision feedback equalization
- VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
- DFI 5.0-compliant controller interface
- Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution
| Description: | DDR5/4 PHY - SS 10LPP |
| Name: | dwc_ddr54_phy_ss10lpp |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores DD5/4 PHY Interconnect Signal and Power Integrity Guidelines DesignWare Cores DDR54 PHY PHYInit Software Overview Application NoteDatabooks DesignWare Cores DD5/4 PHY Databook DesignWare Cores DD5/4 PHY Utility Block Databook (PUB)Implementation Guide DesignWare Cores DD5/4 PHY Implementation GuideRelease Notes  DesignWare Cores DD5/4 PHY Release Notes |
| Download: | DDR5-PHY_SS_10LPP |
| Product Code: | D776-0 |
| Description: | DDR5/4 PHY - SS 7LPP |
| Name: | dwc_ddr54_phy_ss7lpp |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | DDR5-PHY_SS_7LPP |
| Product Code: | D777-0 |
| Description: | DDR5/4 PHY - TSMC 16FFC |
| Name: | dwc_ddr5_4_phy_tsmc16ffc |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Description: | DDR5/4 PHY - TSMC N7 |
| Name: | dwc_ddr54_phy_tsmc7ff18 |
| Version: | 1.10a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | DDR5-4-PHY_TSMC_N7 |
| Product Code: | D220-0 |