The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 8400 Mbps. The DesignWare DDR5/4 PHY is ideal for systems that require high-speed, high-performance, and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB)that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
DesignWare DDR5/4 PHY IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 8400 Mbps
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/ frequencies with <3μs switching time
- I/O receiver decision feedback equalization
- VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
- DFI 5.0-compliant controller interface
- Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution
| Description: |
DDR5/4 PHY - GF 12LP+ |
| Name: |
dwc_ddr54_phy_gf12lpp18 |
| Version: |
1.00a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
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| Product Type: |
DesignWare Cores |
| Documentation: |
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Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware ATE Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware Training Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.40a) ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for GF12LPP18 (PHY Version: 1.00a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version: 3.40a) ( PDF | HTML )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR5/4 PHY Release Notes for GF12 LPP18 (PHY Version 1.00a) ( TXT )
|
| Download: |
dwc_ddr54_phy_gf12lpp18 |
| Product Code: |
F757-0 |
| | |
| Description: |
DDR5/4 PHY - LRDIMM Add-On |
| Name: |
dwc_ddr54_phy_lrdimm_add_on |
| Version: |
F-2022.01 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
|
| Download: |
dwc_ddr54_phy_lrdimm_add_on |
| Product Code: |
F967-0 |
| | |
| Description: |
DDR5/4 PHY - SS 10LPP |
| Name: |
dwc_ddr54_phy_ss10lpp |
| Version: |
1.21a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware ATE Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware Training Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for SS10LPP (PHY Version: 1.21a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( HTML | PDF )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 0.35a) ( PDF | HTML )
Release Notes DesignWare Cores DDR5/4 PHY Release Notes (PHY Version 1.21a) ( TXT )
|
| Download: |
dwc_ddr54_phy_sams10lpp18 |
| Product Code: |
D776-0 |
| | |
| Description: |
DDR5/4 PHY - SS 7LPP |
| Name: |
dwc_ddr54_phy_ss7lpp |
| Version: |
1.11b |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware ATE Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware Training Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for SAMS7LPP18 (PHY Version:1.11b) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( HTML | PDF )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 0.35a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 PHY Release Notes (PHY Version:1.11b) ( TXT )
|
| Download: |
dwc_ddr54_phy_sams7lpp18 |
| Product Code: |
D777-0 |
| | |
| Description: |
DDR5/4 PHY - TSMC 12FFC |
| Name: |
dwc_ddr54_phy_tsmc12ffc |
| Version: |
1.11a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines ( PDF )
DesignWare Cores DDR5/4 PHY CTB and Verification Application Note (CTB Version: … ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Training Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.40a) ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC12FFC18 (PHY Version: 1.11a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version: 3.40a July 13, 2021) ( PDF | HTML )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR5/4 PHY Databook for TSMC12FFC18 Release Notes (PHY … ( TXT )
|
| Download: |
dwc_ddr54_phy_tsmc12ffc18 |
| Product Code: |
D779-0 |
| | |
| Description: |
DDR5/4 PHY - TSMC 16FFC |
| Name: |
dwc_ddr54_phy_tsmc16ffc |
| Version: |
1.11a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2021.07) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY CTB and Verification Application Note (Version 1.00a) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Firmware Training Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Training Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.40a) ( PDF | HTML )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC16FFC18 (PHY Version: 1.11a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version: 3.40a July 13, 2021) ( PDF | HTML )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR5/4 PHY Databook for TSMC16FFC18 Release Notes (PHY … ( TXT )
|
| Download: |
dwc_ddr54_phy_tsmc16ffc |
| Product Code: |
D778-0 |
| | |
| Description: |
DDR5/4 PHY - TSMC N5 |
| Name: |
dwc_ddr54_phy_tsmc5ff12 |
| Version: |
2.40b |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY CTB and Verification Application Note (Version 1.00a) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Firmware ATE Application Note (FW Version: … ( PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version: 3.30b) ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC5FF12 (2.40a July 2021) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version: 3.30a) ( PDF | HTML )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 PHY Release Notes for TSMC5FF12 (PHY Version:2.40a) ( TXT )
|
| Download: |
dwc_ddr54_phy_tsmc5ff12 |
| | |
| Description: |
DDR5/4 PHY - TSMC N7 |
| Name: |
dwc_ddr54_phy_tsmc7ff18 |
| Version: |
1.40a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2021.07) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY CTB and Verification Application Note (CTB Version: … ( HTML )
DesignWare Cores DDR5/4 PHY DDR5 UDIMM/RDIMM Training Firmware Application … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Training Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY Databook for TSMC7FF18 (PHY Version: 1.40a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Utility Block Databook (PUB Version 1.01a) ( HTML | PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 PHY Release Notes (PHY Version: 1.40a) ( TXT )
|
| Download: |
dwc_ddr54_phy_tsmc7ff18 |
| | |
| Description: |
DDR5/4 PHY V2 - TSMC N5 |
| Name: |
dwc_ddr54_phy_v2_tsmc5ff12 |
| Version: |
1.10a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2021.07) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY CTB and Verification Application Note (CTB Version: … ( PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Training Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version:4.10a) ( PDF )
Databooks DesignWare Cores DDR5/4 PHY V2 Databook for TSMC5FF12 (PHY Version: 1.10a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY V2 Utility Block Databook (PUB Version: 4.10a July 2021) ( PDF | HTML )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 V2 PHY Release Notes for TSMC5FF12 (PHY Version: 1.10a) ( TXT )
|
| Download: |
dwc_ddr54_phy_v2_tsmc5ff12 |
| Product Code: |
F451-0 |
| | |
| Description: |
DDR5/4 PHY V2 - TSMC N6 |
| Name: |
dwc_ddr54_phy_v2_tsmc6ff18 |
| Version: |
1.30a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2021.07) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY CTB and Verification Application Note (CTB Version: … ( PDF | HTML )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Training Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY V2 IBIS Model Application Note (Version 1.30a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version:4.10a) ( HTML | PDF )
Databooks DesignWare Cores DDR5/4 PHY V2 Databook for TSMC6FF18 (PHY Version: 1.30a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY V2 Utility Block Databook (PUB Version: 4.10a July 2021) ( PDF | HTML )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 PHY V2 Release Notes for TSMC6FF18 (PHY Version:1.30a) ( TXT )
|
| Download: |
dwc_ddr54_phy_v2_tsmc6ff18 |
| Product Code: |
F752-0 |
| | |
| Description: |
DDR5/4 PHY V2 - TSMC N7 |
| Name: |
dwc_ddr54_phy_v2_tsmc7ff18 |
| Version: |
2.50a |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR5/4 PHY Interconnect Signal and Power Integrity Guidelines … ( PDF )
DesignWare Cores DDR5/4 PHY ATE Firmware Application Note (FW Version: F-2021.07) ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Diagnostics Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY OCC implementation using internal PLL Application … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY PHYInit Software Overview Application Note ( HTML | PDF )
DesignWare Cores DDR5/4 PHY Training Firmware Application Note (FW Version: … ( HTML | PDF )
DesignWare Cores DDR5/4 PHY V2 IBIS Model Application Note (Version 1.30a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY coreKit User Guide (coreKit Version:4.10a) ( HTML | PDF )
DesignWare Cores DDRn Power Integrity and Supply Impedance Determination for DDR … ( PDF )
Databooks DesignWare Cores DDR5/4 PHY V2 Databook for TSMC7FF18 (PHY Version: 2.50a) ( PDF | HTML )
DesignWare Cores DDR5/4 PHY V2 Utility Block Databook (PUB Version: 4.10a July 2021) ( PDF | HTML )
Datasheet DesignWare DDR5/4 PHY IP Datasheet ( PDF )
Implementation Guide DesignWare Cores DDR5/4 PHY Implementation Guide (Version: 2.40a) ( PDF | HTML )
Release Notes DesignWare Cores DDR54 PHY V2 Release Notes for TSMC7FF18 (PHY Version: 2.50a) ( TXT )
|
| Download: |
dwc_ddr54_phy_v2_tsmc7ff18 |
| Product Code: |
F450-0 |
