DesignWare DDR multiPHY IP

Synopsys DesignWare® DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.25V DDR3), DDR2, LPDDR, and LPDDR2 SDRAM memories up to 1066 Mbps data rates. The DDR multiPHY is an area- and feature-optimized PHY that is ideal for designers who require flexibility in regard to the type and number of DDR interfaces for their SoCs. Once implemented in the chip, the DDR multiPHY allows the specific DDR type supported in a system to be programmed via simple software control.

The DesignWare DDR multiPHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a master and slave DLL library, and Synopsys' unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based controller logic and the hard PHY IP.

The DDR multiPHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching. A key component of the DesignWare DDR multiPHY is the PHY Utility Block (PUBL) that is supplied as soft IP. The PUBL contains the circuitry to provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.

DesignWare DDR multiPHY Datasheet

Highlights

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Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
When combined with a DesignWare Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
Compatible with the DesignWare DDR PHY Compiler

GUI-based tool used to assemble a customized DDR PHY targeting a specific application

Scalable architecture that supports from 0 to 1066 Mbps
DFI 2.1 interface to controller
Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries

All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.), while simultaneously taking all the difficult timing closure out of the user's hands.

Support for package on package (PoP) designs

The PHY can be broken up and distributed around the die if required for PoP connectivity

Uses only 4 layers of metal for ITM and DLL
Uses only 6 layers of metal for I/O cells
Low latency
Precision analog DLLs results in ultra-low jitter

Master DLL component for SDRAM command generation and general host timing
Master/slave DLL component for SDRAM write data generation and read data capture
Immune to PVT variation
Uses core voltage level

Real time DQS drift detection and compensation
Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
Permits operating with SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
At-speed loopback test mode for production test
Low area and low power architecture
Application specific multi-protocol DDR I/O library featuring PVT independent ZQ/RZQ programmable ODT and drive strength

Includes calibration controller logic
Includes power, spacer, and corner cells

Area-optimized I/O

Staggered I/O supported
Supports circuit under pad (CUP) and bond over active (BOA)
Supports flip chip and wire bond

I/O retention mode

Maintains I/O drive state during VDD power down
Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode

Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments

DDR multiPHY - FUJ 40LP25	STARs	Subscribe
Gen2 DDR multiPHY - SMIC 28HKMG	STARs	Subscribe
DDR multiPHY - GF 28SLP18	STARs	Subscribe
DDR multiPHY - GF 40LP25	STARs	Subscribe
DDR multiPHY - IBM 28LP18	STARs	Subscribe
DDR multiPHY - SMIC 40LL25	STARs	Subscribe
DDR multiPHY - SMIC 65LL25	STARs	Subscribe
DDR multiPHY - TSMC 40LP25	STARs	Subscribe
DDR multiPHY - TSMC 40ULP25	STARs	Subscribe
DDR multiPHY - UMC 40LP25	STARs	Subscribe

Description:	DDR multiPHY - FUJ 40LP25
Name:	dwc_ddr_multiphy_fuj40lp25
Version:	1.00b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	DDR-m-PHY_FUJ_40LP25
Product Code:	C222-0

Description:	DDR multiPHY - GF 28SLP18
Name:	dwc_ddr_multiphy_gf28slp18
Version:	2.10a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR multiPHY Release Notes
Download:	DDR-m-PHY_GF_28SLP18
Product Code:	9139-0

Description:	DDR multiPHY - GF 40LP25
Name:	dwc_ddr_multiphy_gf40lp25
Version:	2.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR multiPHY Release Notes
Download:	DDR-m-PHY_GF_40LP25
Product Code:	4784-0

Description:	DDR multiPHY - IBM 28LP18
Name:	dwc_ddr_multiphy_ibm28lp18
Version:	2.10a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR2/3-Lite/mDDR SDRAM PHY Databook Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR2/3-Lite/mDDR SDRAM PHY Release Notes
Download:	DDR-m-PHY_IBM_28LP18
Product Code:	4785-0

Description:	DDR multiPHY - SMIC 40LL25
Name:	dwc_ddr_multiphy_smic40ll25
Version:	2.30a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR multiPHY Release Notes
Download:	DDR-m-PHY_SMIC_40LL25
Product Code:	4792-0

Description:	DDR multiPHY - SMIC 65LL25
Name:	dwc_ddr_multiphy_smic65ll25
Version:	2.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR multiPHY Release Notes
Download:	DDR-m-PHY_SMIC_65LL25
Product Code:	4786-0

Description:	DDR multiPHY - TSMC 40LP25
Name:	dwc_ddr_multiphy_tsmc40lp25
Version:	2.30a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR multiPHY Release Notes
Download:	DDR-m-PHY_TSMC_40LP25
Product Code:	7605-0

Description:	DDR multiPHY - TSMC 40ULP25
Name:	dwc_ddr_multiphy_tsmc40ulp25
Version:	1.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn Read Data Eye Training Application Note DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide
Download:	DDR-m-PHY_TSMC_40ULP25
Product Code:	C277-0

Description:	DDR multiPHY - UMC 40LP25
Name:	dwc_ddr_multiphy_umc40lp25
Version:	1.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DWC Power Integrity and Supply Impedance Determination for DDR Interfaces Application … DesignWare Cores DDR2/1 SDRAM PHY Interfacing with Third-Party Controllers DesignWare Cores DDRn SDRAM PHY Implementation Checklist DesignWare Cores Power Integrity and Supply Impedance Determination for DDR … Databooks DesignWare Cores DDR SDRAM PHY Utility Block Lite (PUBL) Databook DesignWare Cores DDR multiPHY Databook Datasheet DesignWare DDR Complete Solution Datasheet Implementation Guide DesignWare Core DDR SDRAM PHY Implementation Guide Installation Guide DesignWare Core DDR SDRAM PHY Installation Guide Release Notes DesignWare Cores DDR multiPHY Release Notes
Download:	DDR-m-PHY_UMC_40LP25
Product Code:	A267-0

Description:	Gen2 DDR multiPHY - SMIC 28HKMG
Name:	dwc_ddr_multiphy_g2_smic28hkmg18
Version:	1.20a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Note DesignWare Cores Power Integrity and Supply Impedance Determination for DDR …
Download:	DDR-G2-m-PHY_SMIC_28HKMG
Product Code:	C404-0