DesignWare DDR multiPHY IP

Synopsys DesignWare® DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.25V DDR3), DDR2, LPDDR, and LPDDR2 SDRAM memories up to 1066 Mbps data rates. The DDR multiPHY is an area- and feature-optimized PHY that is ideal for designers who require flexibility in regard to the type and number of DDR interfaces for their SoCs. Once implemented in the chip, the DDR multiPHY allows the specific DDR type supported in a system to be programmed via simple software control.

The DesignWare DDR multiPHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a DLL library, and Synopsys' unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based controller logic and the hard PHY IP.

The DDR multiPHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching. A key component of the DesignWare DDR multiPHY is the PHY Utility Block (PUBL) that is supplied as soft IP. The PUBL contains the circuitry to provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.

DesignWare DDR multiPHY Datasheet