DesignWare® DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standard DDR5 and DDR4 SDRAMs and DIMMS. The highly configurable controller meets or exceeds the design requirements of a wide range of applications from data center to consumer. The DesignWare DDR5/4 Controller connects to the DesignWare DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution. The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.
The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
DesignWare DDR5/4 Controller IP Datasheet
Downloads and Documentation
- Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to DesignWare DDR5/4 PHY or other DDR5/4 PHYs
- Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
- High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
- UVM testbench with embedded assertions and options to incorporate a DDR5/4 PHY into a verification environment
|DDR Controller supporting DDR5 and DDR4 with advanced features package||STARs
|DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package||STARs
|DDR Controller supporting DDR5 and DDR4 with a CHI interface||STARs