2024-11-27 12:44:33
Synopsys DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standard DDR5 and DDR4 SDRAMs and DIMMS. The highly configurable controller meets or exceeds the design requirements of a wide range of applications from data center to consumer. The Synopsys DDR5/4 Controller connects to the Synopsys DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution. The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.
The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
The Synopsys DDR Controller seamlessly integrates the Synopsys
Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. Synopsys Secure DDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the Synopsys secure memory controllers is as low as 2 clock cycles.
Learn about the broad portfolio of Security Solutions for Interfaces.
Synopsys DDR5/4 Controller IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
- Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
- High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
- UVM testbench with embedded assertions and options to incorporate a DDR5/4 PHY into a verification environment
- Secure Controller: Integrated IME Security Module for data confidentiality
| DDR Controller supporting DDR5 and DDR4 | STARs |
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| DDR Controller supporting DDR5 and DDR4 with Advanced Features Package | STARs |
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| DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package | STARs |
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| DDR Controller supporting DDR5 and DDR4 with a CHI interface | STARs |
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| DDR Controller supporting DDR5 with Advanced Features Package | STARs |
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| DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package | STARs |
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| DDR Secure Controller supporting DDR5 | STARs |
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| DDR Low Latency Controller supporting DDR5 | STARs |
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| DDR Controller supporting DDR5 RDIMM and MRDIMM Gen2 with Advanced Feature Package | STARs |
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| Description: |
DDR Controller supporting DDR5 and DDR4 |
| Name: |
dwc_ddr54_controller |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR54 (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5/4 Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5/4 Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/4 Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR/4 Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
E090-0 |
| Description: |
DDR Controller supporting DDR5 and DDR4 with a CHI interface |
| Name: |
dwc_ddr54_controller_chi |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR54 (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5/4 Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5/4 Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/4 Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR/4 Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
E124-0 |
| Description: |
DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package |
| Name: |
dwc_ddr54_controller_afp_chi |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR54 (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5/4 Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5/4 Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/4 Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR/4 Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
E904-0 |
| Description: |
DDR Controller supporting DDR5 and DDR4 with Advanced Features Package |
| Name: |
dwc_ddr54_controller_afp |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR54 (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5/4 Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5/4 Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5/4 Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/4 Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR/4 Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5/4 Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
E091-0 |
| Description: |
DDR Controller supporting DDR5 RDIMM and MRDIMM Gen2 with Advanced Feature Package |
| Name: |
dwc_ddr5_mrdimm2_controller_afp |
| Version: |
1.72a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Databook Synopsys Controller IP DDR5 MRDIMM2 Controller Databook (Version: 1.72a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5 MRDIMM2 Controller Installation Guide (Version: 1.72a-lca00) ( PDF | HTML )
Reference Manual Synopsys Controller IP DDR5 MRDIMM2 Controller Reference Manual (Version: 1.72a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5 MRDIMM2 Controller Release Notes (Version: 1.72a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5 MRDIMM2 Controller Solution Subsystem User Guide (Version: 1.72a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr5_mrdimm2 |
| Product Code: |
I610-0 |
| Description: |
DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package |
| Name: |
dwc_ddr5_controller_afp_chi |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR5 (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5 Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5 Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5 Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5 Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5 Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR5 Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
H311-0 |
| Description: |
DDR Controller supporting DDR5 with Advanced Features Package |
| Name: |
dwc_ddr5_controller_afp |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR5 (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5 Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5 Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5 Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5 Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5 Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR5 Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
H310-0 |
| Description: |
DDR Low Latency Controller supporting DDR5 |
| Name: |
dwc_ddr5_ll_controller |
| Version: |
1.71a-lca00 |
| ECCN: |
3E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare Cores DDR Controller DDR5 MR4 Wide Range Application Note (Doc Version: 1.00a; DDRCTL Version: 1.41a-lca02) ( PDF | HTML )
DesignWare Cores DDRCTL Implementation Guide for DDR5LL (Version: 1.00a) ( PDF | HTML )
Synopsys Controller IP DDR5 Controller Maximum Setting of RFSHMOD0.refresh_burst Application Note (Version: 1.00a) ( PDF | HTML )
Synopsys IP Basic Core Module Synchronizers Application Note, Version 2024.12 ( PDF | HTML )
Databooks Synopsys Controller IP DDR5 Low Latency Memory Controller Change-Tracked Databook (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Low Latency Memory Controller Databook (Version: 1.71a-lca00) ( PDF | HTML )
Installation Guide Synopsys Controller IP DDR5 Low Latency Memory Controller Installation Guide (Version: 1.71a-lca00) ( PDF | HTML )
Reference Manuals Synopsys Controller IP DDR5 Low Latency Memory Controller Change-Tracked Reference Manual (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Low Latency Memory Controller Reference Manual (Version: 1.71a-lca00) ( PDF | HTML )
Release Notes Synopsys Controller IP DDR5 Low Latency Memory Controller Release Notes (Version: 1.71a-lca00) ( PDF | HTML )
User Guides Synopsys Controller IP DDR/LPDDR SINIT/CINIT Change-Tracked User Guide (Doc Version: 4.40a) ( PDF )
Synopsys Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.40a) ( PDF | HTML )
Synopsys Controller IP DDR5 Low Latency Memory Controller Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Low Latency Memory Controller Solution Subsystem Change-Tracked User Guide (Version: 1.71a-lca00) ( PDF )
Synopsys Controller IP DDR5 Low Latency Memory Controller Solution Subsystem User Guide (Version: 1.71a-lca00) ( PDF | HTML )
Synopsys Controller IP DDR5 Low Latency Memory Controller User Guide (Version: 1.71a-lca00) ( PDF | HTML )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr54 |
| Product Code: |
H309-0 |
| Description: |
DDR Secure Controller supporting DDR5 |
| Name: |
dwc_ddr5_ime_controller |
| Version: |
1.51a-lca00 |
| ECCN: |
5D002.b2/ENC |
| STARs: |
Open and/or Closed STARs |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Databook Synopsys Controller IP DDR5 Secure Memory Controller Databook (Version: 1.51a-lca00) ( PDF )
Installation Guide Synopsys Controller IP DDR5 Secure Memory Controller Installation Guide (Version: 1.51a-lca00) ( PDF )
Reference Manual Synopsys Controller IP DDR5 Secure Memory Controller Reference Manual (Version: 1.51a-lca00) ( PDF )
Release Notes Synopsys Controller IP DDR5 Secure Memory Controller Release Notes (Version: 1.51a-lca00) ( PDF )
User Guides Synopsys Controller IP DDR5 Secure Memory Controller Solution Subsystem User Guide (Version: 1.51a-lca00) ( PDF )
Synopsys Controller IP DDR5 Secure Memory Controller User Guide (Version: 1.51a-lca00) ( PDF )
|
| Toolsets: |
Qualified Toolsets |
| Download: |
dw_iip_DWC_ddrctl_ddr5_secure |
| Product Code: |
H809-0 |
