- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
< Silicon Design & Verification
Silicon Design & Verification
< Products
< Products
< Products
< Products
< Products
< Products
< Products
< Silicon Design & Verification
< Solutions
< Solutions
< Solutions
Cloud
Synopsys in the Cloud
< Solutions
< Solutions
< Silicon Design & Verification
< Resources
< Resources
Verification
Articles
Blogs
Datasheets
Events
News
Newsletters
Success Stories
Videos
Webinars
White Papers
< Resources
< Silicon Design & Verification
< Services
< Services
< Services
< Silicon Design & Verification
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Silicon Design & Verification
< Training
< Silicon Design & Verification
Training
Training and Education
< main menu
< Silicon IP
Silicon IP
< Products
< Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Products
Memories & Libraries
Logic Libraries
Memory Compilers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Products
< Products
Analog IP
Data Converters
< Products
< Products
< Products
< Silicon IP
< Markets
< Silicon IP
Newsletter
< Silicon IP
Customer Success
< Silicon IP
News
< Resources
< Resources
< main menu
< Software Integrity
Polaris Platform
Comprehensive application security from developer to deployment
< Software Integrity
< Software Integrity
< Software Integrity
Professional Services
Strategy and programs that address security before, during and after development
< Software Integrity
< Tools
< Tools
< Tools
< Tools
< Software Integrity
< Services
Managed Security Testing
Managed SAST
Dynamic Analysis (DAST)
Penetration Testing
Mobile Application Security Testing
Network Security Testing
< Services
Professional Services
Strategy and Planning
Architecture & Design
DevSecOps Integration
Cloud Security
Industry Solutions
< Services
< Software Integrity
< Training
< Training
Product Education
< Training
Community
< Software Integrity
< Solutions
< Solutions
< Resources
< Resources
< Software Integrity
< Software Integrity
Customers
< Partners
< Partners
Become a partner
< Software Integrity
< Software Integrity
Blog
< main menu
< About Us
Company
< About Us
< About Us
About Us
About Us
< Investor Relations
< About Us
Investor Relations
Investor Relations
< Community
< About Us
Community
Community
< Newsroom
< About Us
Newsroom
Newsroom
< Resources
< About Us
Resources
Resources
< Careers
< About Us
Careers
Careers
< main menu
DesignWare HBM IP Solution
Advanced graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the increasing compute performance brought by advanced process technologies. With the DesignWare HBM2/HBM2E IP solution, designers can achieve their memory throughput requirements with minimal power consumption and low latency.
The complete DesignWare HBM2/HBM2E IP solution includes controller, PHY and verification IP, enabling designers to achieve up to 409 GBps aggregate bandwidth, which is over 14 times the bandwidth of a 72-bit DDR4 interface operating at up to 3200 Mbps. In addition, the DesignWare HBM2/HBM2E IP solution delivers approximately 10X better energy efficiency than DDR4. The DesignWare HBM2/HBM2E IP solution leverages elements from Synopsys’ silicon-proven DDR4 IP, which has been validated in hundreds of designs and shipped in millions of systems-on-chips (SoCs), enabling designers to lower integration risk and accelerate adoption of the new standard. In addition, DesignWare HBM IP is in volume production with numerous customer SoCs. The DesignWare HBM2/HBM2E PHY is provided as a set of hard macrocells delivered as GDSII along with a soft PHY Utility Block (PUB). The hard macrocells include integrated application-specific HBM2/HBM2E I/Os required for HBM2/HBM2E signaling and are easily assembled into a complete 512- or 1,024-bit HBM2/HBM2E PHY. The PUB provides the PHY configuration registers, training algorithms, and BIST features of the interface. The design is optimized for high performance, low latency, low area, low power, and ease of integration.
Figure 1: DesignWare HBM2/HBM2E PHY IP Block Diagram
In select process technologies, Synopsys also offers pre-hardened HBM2/HBM2E PHY options. For designers with unique requirements, Synopsys also offers services to harden a DDR/HBM PHY to meet exact target requirements including metal stack, decoupling parameters, etc.
DesignWare HBM2/HBM2E PHY Datasheet
Highlights
Products
Downloads and Documentation
- Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
- 2.5D interposer expertise and reference designs
- Supports 2.5D-based JEDEC standard HBM2/HBM2E SDRAMs with data rates up to 3200 Mbps
- Up to 2400 Mbps with HBM2
- Up to 3600 Mbps with HBM2E
- Pseudo-channel mode doubles the number of channels, resulting in smaller fetch size and higher performance
- The HBM2/HBM2E IP is based on Synopsys’ silicon-proven HBM and DDR4 IP that has been integrated into hundreds of SoC designs
- DFI 4.0-compatible interface
- PHY independent training capability
- Comprehensive set of design-for-test (DFT) features
| Description: | HBM2 PHY - TSMC 16FF+GL |
| Name: | dwc_hbm2_phy_tsmc16ffpgl |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Description: | HBM2 PHY - TSMC 16FF+LL18 |
| Name: | dwc_hbm2_phy_tsmc16ffpll18 |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Databooks DesignWare Cores HBM2 PHY Databook DesignWare Cores HBM2 PHY Utility Block (PUB)Datasheet DesignWare HBM2/HBM2E PHY DatasheetImplementation Guide DesignWare Cores HBM2/2e Implementation GuideRelease Notes  DesignWare Cores HBM2 PHY Release Notes |
| Download: | HBM2-PHY_TSMC_16FFPLL |
| Product Code: | C519-0 |
| Description: | HBM2 PHY - TSMC 16FFC |
| Name: | dwc_hbm2_phy_tsmc16ffc18 |
| Version: | 1.10a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | HBM2-PHY_TSMC_16FFC |
| Product Code: | D889-0 |
| Description: | HBM2 PHY - TSMC 7FF18 |
| Name: | dwc_hbm2_phy_tsmc7ff18 |
| Version: | 1.50b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Databooks DesignWare Cores HBM2 PHY Databook DesignWare Cores HBM2 PHY Utility Block (PUB)Datasheet DesignWare HBM2/HBM2E PHY DatasheetImplementation Guide DesignWare Cores HBM2/2e Implementation GuideRelease Notes DesignWare Cores HBM2 PHY Release Notes |
| Download: | HBM2-PHY_TSMC_N7 |
| Product Code: | C407-0 |
| Description: | HBM2E PHY (Hard 1) - TSMC 7FF18 |
| Name: | dwc_hbm2e_phy_hard1_tsmc7ff18 |
| Version: | 1.00a-EW-Hardened |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | Hard-HBM2E-PHY_TSMC_N7 |
| Product Code: | E380-0 |
| Description: | HBM2E PHY - TSMC 7FF18 |
| Name: | dwc_hbm2e_phy_tsmc7ff18 |
| Version: | 1.20a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Databooks DesignWare Cores HBM2e PHY Databook DesignWare Cores HBM2e PHY Utility Block (PUB)Implementation Guide DesignWare Cores HBM2/2e Implementation GuideRelease Notes DesignWare Cores HBM2e PHY Release Notes |
| Download: | HBM2E-PHY_TSMC_N7 |
| Product Code: | D782-0 |