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VCS® Verification Library

The VCS Verification Library, containing DesignWare® Verification IP (VIP), provides a broad portfolio of design-proven, standards-based VIP to dramatically speed testbench development time and achieve functional coverage goals faster. It now supports the constrained-random, coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog and is an integral part of the Synopsys Discovery™ Platform. In addition, the verification IP supports Native Testbench in VCS to deliver up to 5X improvement in runtime performance.

The VCS Verification Library is the industry’s broadest portfolio of standards-based verification IP, which easily integrate Verilog, SystemVerilog, VHDL and OpenVera® testbenches.

  Press Releases
SystemVerilog Dot Synopsys Announces EDA Industry’s First Verification IP Library for SystemVerilog with Methodology Support
  White Papers
SystemVerilog Dot Five Vital Steps to a Robust Testbench with DesignWare Verification IP and the Verification Methodology Manual (VMM) for SystemVerilog
SystemVerilog Dot Advanced Techniques for Robust Testbench Development with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
SystemVerilog Dot DesignWare Verification IP support of the VMM for SystemVerilog reduces time to first test for coverage-driven verification.
  For More Information
SystemVerilog Dot For more product information and to download DesignWare Verification IP with SystemVerilog