EDA
System
IP
SolvNetPlus
Training & Education
Shift Left to Ship Faster: Verifying IP and SoCs at Real Workload Speeds
Featured Speakers:
- Madhumita Sanyal, Sr. Director of Technical Product Management, Synopsys
- Varun Agrawal, Director of Product Management, Synopsys
As SoC complexity climbs, traditional verification can't keep pace — and system-level bugs surface late, when they're hardest to fix. By pairing Hardware-Assisted Verification (HAV) with Interface IP like PCIe, Ethernet, and DDR, teams validate earlier and at far higher performance, catching issues well before tape-out.
Join Synopsys experts to see how Interface IP, VIP, and HAV work together to accelerate validation and speed silicon bring-up.
What you'll learn:
- How HAV and Interface IP shift verification left at real workload speeds
- How to run real software workloads to boost debug productivity and cut integration risk
- How to keep full coverage across PCIe, Ethernet, and other high-speed interfaces
Register Now
Featured Speakers
Madhumita Sanyal
Sr. Director of Technical Product Management, Synopsys
Madhumita Sanyal is a senior Director of Technical Product Management specializing in advanced interface technologies, C2C interconnects, and system architecture for next-generation computing platforms. She has 23+ years of experience in the design, and product management of high-speed I/O, system-level design, SoCs with a focus on enabling scalable solutions for AI, data center, and high-performance computing. More >
Varun Agrawal
Director of Product Management, Synopsys
Varun Agrawal is a product manager for verification IP, virtual system adaptors, and protocol solutions for hardware-assisted platforms at Synopsys. He has over 14 years of experience in functional verification with expertise in simulation, emulation, and virtualization domains. More >
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