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Synopsys DesignWare DigRF v4 Master Controller IP Solution

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The MIPI DigRF interface is a high speed, serial, digital chip to chip interface and communication protocol between Baseband processor ICs and RF IC enabling increased reliability, lower power, lower pin count and increased interoperability.

The MIPI DigRF v4 specification is based on a scalable architecture. This architecture provides significantly higher bandwidth than the DigRF 3G version and relies on the MIPI M-PHY as a physical layer. It is intended to be used in mobile terminals that support high bandwidth mobile broadband technologies such as LTE and Mobile WiMax.

The DesignWare DigRF v4 Master Controller IP core implements all the functionalities defined for the protocol layer of the DigRF v4 interface. It is fully configurable to enable support for 1 TX Channel and up to 2 RX Channels and can be used for basic handset configurations as well as with local and remote diversity.

DesignWare DigRF v4 Master Controller Datasheet
DesignWare MIPI Complete Solution Datasheet
 



Demo of DesignWare MIPI DigRFv4 and
M-PHY IP

Demo of proven system-level interoperability using Synopsys' DesignWare MIPI DigRFv4 and MIPI
M-PHY IP solutions.

  • Configurable Master Controller for MIPI DigRF v4 interface
  • Compliant with MIPI Alliance Specification for DigRFSM v4, Version 0.64.00, 1.00.00 and 1.10.00
  • Frame construction, serialization and scheduling in the Transmit channel
  • Header decoding and payload processing in the Receive channel.
  • PHY interface compliant with MIPI M-PHY Signaling Interface
  • Standard AMBA APB interface for configuration, control and status
  • Support for 1 TX Lane, and 1 or 2 RX Lanes Interface with external FIFO memories for data buffering, and configurable size
  • Configurable I/Q sample format
  • System Data Interface using I/Q sample interface, supporting up to 16-bit per sample
  • Supports Low Speed (LS), High Speed 1x Primary (HS1P) and High Speed 1x Secondary (HS1S) modes
  • Supports Automatic Repeat reQuest (ARQ) management;
  • Support up to 8 sources for Time Accurate Strobe (TAS) messages
  • Supports HS-Burst Dithering
  • Supports randomized IDLE symbols
  • Support for multiple test modes
  • Support for Link Test Modes: Ping Message, Clock Test Mode and Line Loopback Mode