DesignWare MIPI CSI-2 Host and Device Controller IP Solutions

Integrating advanced peripherals such as multi-megapixel cameras and higher resolution screens into next generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs. To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes system-on-chip (SoC) and peripheral device interface specifications, such as the Camera Serial Interface (CSI-2).

Compliant with the latest MIPI CSI-2 specification, DesignWare® MIPI CSI-2 Host and Device Controllers are fully-verified configurable IP solutions that provide a high-speed serial interface between an application or image processor and camera sensors. The controllers are architected to interface with the silicon-proven DesignWare MIPI D-PHY IP via the recommended PHY Protocol Interface (PPI), providing an easy to integrate and high-quality solution.

Synopsys’ DesignWare MIPI CSI-2 Host Controller IP, DesignWare MIPI CSI-2 Device Controller IP, DesignWare MIPI I3C Controller IP and DesignWare MIPI D-PHY IP provide a complete camera interface IP solution that enables designers to lower the risk and cost of integrating the MIPI CSI-2 interface IP into application processors, image signal processors and multimedia co-processors, while improving the time-to-market demand of mobile, IoT and automotive SoCs.

DesignWare MIPI Complete Solution Datasheet
DesignWare MIPI CSI-2 Device Controller IP Datasheet
DesignWare MIPI CSI-2 Host Controller Datasheet
DesignWare MIPI D-PHY Datasheet
DesignWare MIPI I3C Controller IP Datasheet

 

Highlights
Products
Downloads and Documentation
  • Compliant with the MIPI CSI-2 specification, v1.2
  • PPI interface to D-PHY as recommended in the MIPI D-PHY specification, v1.2
  • Configurable up to 8 data lanes at up to 2.5 Gbps per lane
  • Supports all primary and secondary CSI-2 Data Formats
  • Short and Long packet formats
  • Built-in test and debug capabilities
  • Automatic generation of error correction code for the packet header, and checksum for the packet data
  • Programmable multi-lane merging
  • Detection of low-power and ultra low-power modes
  • 64-bit pixel output format
  • AMBA® APB control and configuration
  • Packaged with Synopsys coreConsultant tool
MIPI CSI-2 Device ControllerSTARs Subscribe
MIPI CSI-2 Host ControllerSTARs Subscribe
IP Prototyping Kit for DWC MIPI CSI-2 Host Controller on HAPS-DX7, D-PHY card, AXI tunnel to ARC SDPSTARs Subscribe

Description: IP Prototyping Kit for DWC MIPI CSI-2 Host Controller on HAPS-DX7, D-PHY card, AXI tunnel to ARC SDP
Name: dwipk_csi2host_dphy_arc
Version: 2.14a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: ipk_MIPI-CSI2-Host-D-PHY_ARC
Product Code: HW0269-0
  
Description: MIPI CSI-2 Device Controller
Name: dwc_mipicsi2_device
Version: 1.10a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Toolsets: Qualified Toolsets
Download: MIPI-CSI2-DEV-CTLR
Product Code: B148-0
  
Description: MIPI CSI-2 Host Controller
Name: dwc_mipi_csi2_host
Version: 1.20a
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Toolsets: Qualified Toolsets
Download: MIPI-CSI2-Host-CTLR
Product Code: 7609-0