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DesignWare MIPI UniPro Controller IP
The Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile device systems. It is applicable to a wide range of component types including application processors, co-processors, and modems, as well as different types of data traffic including control messages, bulk data transfer and packetized streaming. Implementing the UniPro specification reduces time-to-market and design costs by simplifying the interconnection of peripherals. In addition, the re-useable, extensible nature of the specification simplifies new feature implementation.
Synopsys’ DesignWare® MIPI® UniPro Controller IP, compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a MIPI M-PHY link. Due to its generic nature, the MIPI UniPro Controller IP is capable of transporting any kind of data between applications like camera, display, and memory devices on the same physical link. When the DesignWare MIPI UniPro Controller IP is combined with the DesignWare Universal Flash Storage (UFS) Host Controller IP and DesignWare® MIPI® M-PHY IP, Synopsys provides a single vendor UFS IP solution that designers can easily integrate into application processors with less risk, while speeding time-to-market of advanced SoCs and device integrated circuits (ICs).
DesignWare MIPI Complete Solution Datasheet DesignWare MIPI UniPro Controller Datasheet
Highlights
Products
Downloads and Documentation
- Compliant with the MIPI UniPro v1.8 specification
- Supports all host and device configurations for JEDEC Universal Flash Storage (UFS), and UniPort-M
- Supports HS-Gear4 DesignWare M-PHY IP v4.1 and access to attributes
- HS-Gear4 adaptation and advanced granularity capability
- Low-power operation, small area, and low latency
- Supports clock and power gating using Unified Power Format (UPF)
- Skip symbol insertion, scrambler function, MK2 extension
- Scalable maximum bandwidth (up to 4 lanes in each direction)1
- Configurable number of C Ports and DDB settings