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The Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile device systems. Applicable to a wide range of component types including application processors, co-processors, and modems, as well as different types of data traffic including control messages, bulk data transfer and packetized streaming. Implementing the
UniPro specification reduces time-to-market and design costs by simplifying the interconnection of peripherals. In addition, the re-useable, extensible nature of the specification simplifies new feature implementation.
Synopsys’ DesignWare® MIPI® UniPro Controller IP provides the capability to control
the UniPro link over an M-PHY link. The MIPI UniPro Controller is capable of transporting any
kind of data between applications like camera, display, and memory devices on the same physical link. When combined with the multi-gear DesignWare MIPI M-PHY IP, Synopsys provides a single vendor UniPro-based IP solution, enabling designers to easily integrate the JEDEC UFS, MIPI CSI-3, and MIPI DSI-2 host or device implementation in application processors and peripheral ICs.  DesignWare MIPI Complete Solution Datasheet
DesignWare MIPI UniPro Controller Datasheet
- Compliant with MIPI® Alliance UniPro specification, version 1.60
- Supports all host and device configurations for JEDEC UFS, MIPI UniPort-M, CSI-3 and DSI-2
- Supports HS-Gear3 DesignWare M-PHY v3.0 and access to attributes
- Low-power operation, small area, and low latency
- Enables power gating and use of UPF flow
- HS-Gear3 adaptation and advanced granularity capability
- Skip symbol insertion, scrambler function, MK2 extension
- Scalable maximum bandwidth (up to 4 lanes in each direction)
- Configurable number of C Ports and DDB settings
- Configurable number of C Ports, DDB settings
- Configurable system data interface width
- Generic interface to the application layer
- Automatic flow control
- Reliable transmissions through error detection and automatic retransmission
- Support for up to two traffic classes
- Frame prioritization using pre-emption
- Support for test-modes like scantest and memory BIST
- Configurable number of layer 4 test features
- Generation and check of layer 1.5 test pattern
- Power gating supported
- Use of UPF flow
- Hardware prototyping system available
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