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DesignWare MIPI DSI Host and Device Controller IP Solutions

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Integrating advanced peripherals such as multi-megapixel cameras and high-resolution screens into next generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs. To address these challenges, the MIPI® Alliance defines and promotes system-on-chip (SoC) and peripheral device interface specifications, such as the Display Serial Interface (DSI).

Compliant with the latest MIPI DSI specification, DesignWare® MIPI DSI Host and Device Controllers are fully-verified configurable IP solutions that provide a high-speed serial interface between an application processor and displays. The controllers are architected to interface with the silicon-proven DesignWare MIPI D-PHY IP via the recommended PHY Protocol Interface (PPI), providing an easy to integrate and high-quality solution.

Synopsys’ DesignWare MIPI DSI Host Controller IP, DesignWare MIPI Device Controller IP and DesignWare MIPI D-PHY IP provide a complete display interface IP solution that enables designers to lower the risk and cost of integrating the MIPI DSI interface into application processors, display bridge ICs and multimedia co-processors, while improving the time-to-market demand of mobile, IoT and automotive SoCs.

DesignWare MIPI Complete Solution Datasheet
DesignWare MIPI D-PHY Datasheet
DesignWare MIPI DSI Device Controller IP Datasheet
DesignWare MIPI DSI Host Controller IP Datasheet
 



Synopsys Demonstrates MIPI Camera and Display Prototyping System
Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution.

  • Compliant with the MIPI DSI Specification, v1.2
  • Supports MIPI specifications:
    • Display Pixel Interface (DPI-2) v2.00
    • Display Bus Interface (DSI-2) v2.00
    • Display Command Set (DCS) v1.3
    • Stereoscopic Display Formats (SDF) v1.0
  • Support video and command modes
  • Supports dual MIPI DSI use case with VESA Display Stream Compression (DSC) v1.1 standard
  • Configurable from 1 to 4 data lanes
  • Supports up to 2.5 Gbps per data lane
  • PPI interface to the D-PHY, as recommended in the MIPI D-PHY specification, v1.2
  • Configurable from 1 to 4 data lanes, up to 2.5 Gbps per lane
  • Bi-directional communication and escape mode support
  • Programmable display resolutions
  • Video mode pixel formats: RGB565, RGB666 packed and loosely, RGB888
  • ECC and checksum capabilities
  • Supports ultra-low power mode
  • Fault recovery schemes
  • Multiple peripheral support capability with configurable virtual channels
  • Integrated video pattern generator
  • Supports transmission of all generic commands
  • Configurable selection of system interfaces
  • AMBA® APB control and configuration
  • Packaged with Synopsys coreConsultant tool
MIPI DSI Device ControllerSTARsSubscribe
MIPI DSI Host ControllerSTARsSubscribe

  Description MIPI DSI Device Controller
  Name dwc_mipi_dsi_device
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation Contact Us for More Information
  Product Code
  
  Description MIPI DSI Host Controller
  Name dwc_mipi_dsi_host
  Version 1.31a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_mipi_dsi_host
  Product Code 7610-0