Synopsys IP Prototyping Kits for JEDEC UFS

The Synopsys IP Prototyping Kit for JEDEC UFS centers around a complete, out-of-the-box reference design that consist of a validated IP configuration and necessary SoC integration logic. The software and application examples are implemented on Synopsys’ HAPS®-DX FPGA-based prototyping systems, or they can be delivered separately as files for implementation on your in-house HAPS-80 system.


  • Supports Synopsys UFS Host
  • Power management, clock reset and control block
  • RMMI interface between controller and MIPI M-PHY
  • Pre-instrumented debug for most interfaces
  • IP Prototyping Kits for JEDEC UFS are available in the following configurations:
    • HAPS-DX FPGA-based prototyping systems with PC connection via PCI Express
    • Soft IP Prototyping Kits for use with your in-house HAPS-80 system with ARC SDP