The DesignWare® IP Prototyping Kit for JEDEC UFS centers around a complete, out-of-the-box reference design that consist of a validated IP configuration and necessary SoC integration logic. The software and application examples are implemented on Synopsys’ HAPS®-DX FPGA-based prototyping systems, or they can be delivered separately as files for implementation on your in-house HAPS-80 system.
Table 1: DesignWare IP Prototyping Kits for JEDEC UFS Host
Accelerate UFS Host IP Prototyping & Integration with DesignWare IP Prototyping Kits
Reduce UFS Host IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.
Downloads and Documentation
Supports DesignWare UFS Host
Power management, clock reset and control block
RMMI interface between controller and MIPI M-PHY
Pre-instrumented debug for most interfaces
IP Prototyping Kits for JEDEC UFS are available in the following configurations:
HAPS-DX FPGA-based prototyping systems
With PC connection via PCI Express
With ARC Software Development Platform via AXI
Soft IP Prototyping Kit
For use with your in-house HAPS-80 system
IP Prototyping Kit for DWC UFS 2.X host controller on HAPS-DX7, M-PHY card, AXI tunnel to ARC SDP