The DesignWare® IP Prototyping Kit for JEDEC UFS centers around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system.
With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. The prototyping kit takes advantage of Synopsys’ HAPS Developer eXpress (HAPS-DX) system to provide prototyping hardware and software automation tools. Scripts and configuration files enable fast iteration.
The IP Prototyping Kit can be used as a physical target for early software bring-up, debug and test concurrently with SoC development. Out-of-the-box support for Linux OS and Windows ensures that software developers are up and running instantly and can focus on the IP specific software (e.g., drivers, bootcode, firmware). The kits plugs into existing software tool chains and interfaces seamlessly with popular embedded software debuggers, providing system-wide debug and analysis capabilities.
Accelerate UFS Host IP Prototyping & Integration with DesignWare IP Prototyping Kits
Reduce UFS Host IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.
Downloads and Documentation
DesignWare Universal Flash Storage (UFS) Host
ARM® AMBA® AXI™ Master Bus Interface
AMBA AXI Slave Bus Interface
2x MIPI M-PHY RX lanes
2x MIPI M-PHY TX lanes
Support for Skip Request in RX interface
Power management, clock reset and control block
RMMI interface between controller and MIPI M-PHY
PCI Express® endpoint with AXI interface
Xilinx® 7 Series GTH transceiver PIPE interface
Pre-instrumented debug for most interfaces
IP Prototyping Kit for DWC UFS 2.X host controller on HAPS-DX7, M-PHY card, AXI tunnel to ARC SDP