The DesignWare® SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides advanced features such as ADMA3 for SD 5.0, SDIO 4.10 and Command Queuing Engine for eMMC 5.1 as well as advanced high-performance 32- and 64-bit AXI interface to the SoC.
The IP architecture leverages power management techniques, making it ideal for low-power applications. The highly configurable and scalable IP is packaged with Synopsys coreConsultant tool and is optimized to reduce gate count and power consumption while ensuring compatibility with previous and future generation SD and eMMC standards.
A rigorous UVM-based verification methodology is applied to the DesignWare SD/eMMC Host Controller IP, consisting of directed tests and constrained random verification. The simulation-based verification is further augmented with FPGA hardware verification based on Synopsys’ HAPS®-DX FPGA-based prototyping system. The FPGA development board is tested with all major SD cards, SDIO commands, and eMMC devices. The IP is in volume production and has been successfully implemented in a wide range of applications.
DesignWare SD/eMMC Host Controller IP Datasheet
DesignWare SD/eMMC PHY IP Datasheet
Downloads and Documentation
- Compliant with the SD 5.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
- Advanced eMMC features including HS400 mode and built-in Command Queuing Engine with priority sensitive scheduling algorithm for high performance
- Compliant with host controller interface (HCI) specification for SD ensuring the usability of standard software drivers
- Supports SDMA, ADMA2 and ADMA3 modes
- Includes high-performance 32- and 64-bit AXI bus interface
- Supports UHS-II interface in both full-duplex (FD) and half-duplex (HD) modes and built-in SD-TRANS layers
- Supports multiple options for software-based, software-assisted and hardware-driven tuning
- Available verification IP: SD, eMMC, UHS-II/SD-TRAN