Synopsys’ DesignWare® MIPI I3C Controller IP is compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The support for in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost. The IP is backward compatible with I2C, allowing designers to future proof their design, and the master and slave operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced Peripheral Bus (APB) connects the IP to the rest of the SoC while the bus is connected to the register interface and the Direct Memory Access (DMA) interface, offering easy IP integration.
Low-power management features such as clock gating enable energy-efficient sensors and SoC designs while the configurable transaction and data buffering features enable performance versus cost tradeoffs for the target application.
The DesignWare MIPI I3C Controller IP with Synopsys’ silicon-proven DesignWare MIPI CSI-2 Controller, D-PHY, verification IP and IP Prototyping Kit enable designers to have a complete image sensor interface solution.
DesignWare MIPI I3C Controller IP Datasheet
Downloads and Documentation
- Compliant with the latest MIPI I3C specification
- Supports all data rates up to 33.4 Mbps
- Supports master, secondary master and slave roles
- Supports In-band interrupts within the 2-wire interface
- Dynamic address allocation
- Hot-join capability
- Synchronous/asynchronous time control support
- Low power management support
- 32-bit AMBA APB slave interface to application processor
- Optional simple register access interface
- Configurable external SRAM access
- Peripheral flow control mode and DMA handshaking interface support
- Backward compatible with the I2C slave devices
- Supports multi-master
- Fully interoperable with third-party I3C master and slave solutions