Synopsys MIPI I3C Controller IP is compliant with the I3C specification and delivers higher bandwidth and scalability for integrating multiple sensors into mobile, automotive and IoT system-on-chips (SoCs) that previously depended on I2C. The support for in-band interrupts within the 2-wire interface provides a significantly lower pin count, simplifying board design and reducing power and cost. The I3C electrical characteristics enable faster data rates and lower power consumption than I2C by enabling push-pull mode of operation vs open drain mode in the Clock line and a large portion of the data line. The introduction of Common Command Codes (CCCs) help standardize the communication across controller and targets from different vendors.
The Synopsys Target IP is backward compatible with I2C, allowing designers to future-proof their design whilst still interoperating with legacy and new sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced Peripheral Bus (APB) connects the IP to the rest of the SoC while the bus is connected to the register interface and the Direct Memory Access (DMA) interface, offering easy IP integration.
The Synopsys Target-Lite IP allows for low complexity and cost implementation intended for simple processor-less sensors/actuators to communicate/update their state with a host controller.
Low-power management features such as clock gating enable energy-efficient sensors and SoC designs while the configurable transaction and data buffering features allow performance versus cost trade-offs for the target application.
The Synopsys MIPI I3C Controller IP with Synopsys’ silicon-proven MIPI CSI-2 Controller, D-PHY, verification IP and IP Prototyping Kit enable designers to have a complete image sensor interface solution.
Besides acting as a sensor interface, the Synopsys I3C IP natively supports the JEDEC JESD403-1 specification for DDR5 Sideband communication to connect the Host SoC with PMICs, RCDs and Temperature sensors on RDIMMs.
System Management standards such as Management Component Transport Protocol (MCTP) can be enabled as a layer above the Synopsys I3C IP.
Synopsys has digital IP, IO pads and VIP to make a comprehensive offering for I3C.
Synopsys MIPI I3C Controller IP Datasheet
Downloads and Documentation
- Supports MIPI I3C v1.1.1 specification
- Compliant with MIPI I3C Conformance Test Suite (CTS) v1.0
- Supports the MIPI I3C Host Controller Interface and DDR5 JEDEC JESD403-1 and System Management MCTP specifications
- Supports SDR, HDR-DDR, HDR-TSL/TSP; all data rates up to 33.4 Mbps
- Supports controller, secondary controller and target IP roles
- Supports In-band interrupts within the 2-wire interface
- Dynamic address allocation
- Hot-join capability
- Vendor-specific Command Codes
- Target Reset Pattern
- Asynchronous Timing Control Mode 0
- Virtual targets
- Grouped addressing
- Low power management support
- 32-bit AMBA APB secondary interface to an application processor
- Configurable external SRAM access
- Peripheral flow control mode and DMA handshaking interface support
- Backward compatible with the I2C target IP devices per I3C specification
- Fully interoperable with third-party I3C controllers and target IP solutions
- Proven interoperability with Synopsys I3C IO pads