DesignWare MIPI I3C Controller IP

Synopsys’ DesignWare® MIPI I3C Controller IP is compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The support for in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost. The IP is backward compatible with I2C, allowing designers to future proof their design, and the master and slave operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced Peripheral Bus (APB) connects the IP to the rest of the SoC while the bus is connected to the register interface and the Direct Memory Access (DMA) interface, offering easy IP integration.

Low-power management features such as clock gating enable energy-efficient sensors and SoC designs while the configurable transaction and data buffering features enable performance versus cost tradeoffs for the target application.

The DesignWare MIPI I3C Controller IP with Synopsys’ silicon-proven DesignWare MIPI CSI-2 Controller, D-PHY, verification IP and IP Prototyping Kit enable designers to have a complete image sensor interface solution.

DesignWare MIPI I3C Controller IP Datasheet

 

Highlights
Features
Products
Downloads and Documentation
  • Compliant with the latest MIPI I3C specification
  • Backward compatible with the I2C slave devices
  • Supports all data rates up to 26.7 Mbps
  • In-band interrupts within the 2-wire interface
  • Dynamic address allocation
  • Hot-join capability
  • Low power management support
  • 32-bit ARM AMBA APB slave interface to application processor
  • Configurable external SRAM access
  • Peripheral flow control mode in DMA handshaking interface support
  • Multi-Master support
  • Enables high-bandwidth over low-power 2-wire bus
  • Supports Address Resolution Procedure (ARP)
  • In-band interrupts help keep a very low SoC pin count
  • Separate command register and data buffers for ease of DMA transfers
  • Supports up to 255 Write or Read bytes with a single command
  • Configurable and optional programmable buffer depths
  • Built-in hardware Dynamic Address Allocation (DAA) support
  • Hot-Join capability
  • Fully synthesizable RTL
  • Clock gating-ready design as well as DFT ready
  • Hardware prototyping system available
MIPI I3C Controller for Master and Slave functionalitySTARs Subscribe

Description: MIPI I3C Controller for Master and Slave functionality
Name: dwc_mipi_i3c
Version: 1.00a-lca01
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: MIPI_I3C_Dual_Role_MS
Product Code: B611-0