The DesignWare® Controller IP for M‑PCIe™ implements the port logic required to build a Root Port (RP), Endpoint (EP), Dual Mode (selectable RP/EP), or Switch device. The configurable and scalable DesignWare Controller IP for M‑PCIe is designed to the PCI Express® (PCIe®) 3.0, 2.1, 1.1, M-PCIe ECN and Reference M-PHY Module Interface (RMMI) specifications.
The high-quality, synthesizable Controller integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface and timing. the controller IP is available in a variety of datapath widths, RMMI interface widths, and operating frequencies for optimizing size, power and throughput.
The DesignWare Controller IP for M-PCIe is based on the silicon-proven DesignWare Controller IP for PCI Express, which has been extensively validated with multiple hardware platforms, PHYs and verification suites, providing designers with a high-quality IP that reduces risk and improves time-to-market.
Synopsys offers a portfolio of silicon-proven IP for PCIe consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCIe, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
- Comprehensive M-PCIe IP solution includes a suite of M-PCIe digital controllers and MIPI M-PHY IP
- Support for all required features of the PCIe Base Specification 3.0 in conjunction with the M-PCIe ECN
- Support for all PCIe ports: Root Complex, Endpoint, Dual Mode, and Switch
- Support for x1, x2, x4, x8, and x16 links
- Support for M-PHY Gears 1, 2, and 3
- Synopsys' optional selectable PHY technology allowing one controller instance to support both PCIe PHYs and M-PHY
- RMMI interface for connection to Synopsys or third-party M-PHY IP
- Optimized for low latency, low power, and low gate count
- Application interface options include Native, AMBA 4 AXI, 3 AXI and AHB
- Optional embedded DMA controller