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DesignWare PHY IP for PCI Express 4.0
The multi-channel DesignWare® PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
DesignWare IP for PCI Express Complete Solution Datasheet DesignWare PHY IP for PCI Express 4.0 Datasheet
Highlights
Products
Downloads and Documentation
- Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- Supports lane margining at the receiver
- L1 substate and SRIS support
- Power gating and power island
- Embedded bit error rate (BER) tester and internal eye monitor
- Built-in Self Test vectors, PRBS generation and checker
- IEEE 1149.6 AC JTAG Boundary Scan
- Supports -40C to 125C junction temperatures
- Supports flip-chip packaging
| PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, SS14LPP x1, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 LP PHY, TSMC N6 x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 LP PHY, TSMC N6 x4, North/South (vertical) poly orientation | STARs | Subscribe |
| Description: | PCIe 4.0 LP PHY, TSMC N6 x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4_lp_phy_tsmc6ff_x2ns |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | dwc_pcie4_lp_phy_tsmc6ff_x2ns |
| Product Code: | E990-0 |
| Description: | PCIe 4.0 LP PHY, TSMC N6 x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4_lp_phy_tsmc6ff_x4ns |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | dwc_pcie4_lp_phy_tsmc6ff_x4ns |
| Product Code: | E991-0 |
| Description: | PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_ss14lpp_x4ns |
| Version: | 1.05b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist (Doc Version: 1.00) ( PDF ) DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores 25G PHY IP Integration Review Checklist Application Note (Doc … ( PDF | HTML ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.15) ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Four-Lane PHY for SS 14 LPP Databook (PHY Version: … ( HTML | PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY (PCS Version: 1.41) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Four-Lane PHY for SS 14 LPP Release Notes (PHY … ( TXT ) |
| Download: | dwc_pcie4phy_ss14lpp_x4ns |
| Product Code: | C998-0 |
| Description: | PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_ss11lpp_x1ns |
| Version: | 1.01a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | dwc_pcie4phy_ss11lpp_x1ns |
| Product Code: | E150-0 |
| Description: | PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_ss11lpp_x2ns |
| Version: | 1.01a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | dwc_pcie4phy_ss11lpp_x2ns |
| Product Code: | E151-0 |
| Description: | PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_ss11lpp_x4ns |
| Version: | 1.00a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databook DesignWare Cores PCIe 4.0 Four-Lane PHY for SS 11 LPP Databook (PHY Version: … ( PDF | HTML ) Release Notes DesignWare Cores PCIe 4.0 Four-Lane PHY for SS 11 LPP Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_SS_11LPP_x4 |
| Product Code: | E101-0 |
| Description: | PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_ss14lpp_x2ns |
| Version: | 1.05a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) Databook DesignWare Cores PCIe 4.0 Two-Lane PHY for SS 14 LPP Databook (PHY Version: … ( PDF | HTML ) Release Notes DesignWare Cores PCIe 4.0 Two-Lane PHY for SS 14 LPP Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_SS_14LPP_x2 |
| Product Code: | E097-0 |
| Description: | PCIe 4.0 PHY, SS14LPP x1, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_ss14lpp_x1ns |
| Version: | 1.05a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) Databook DesignWare Cores PCIe 4.0 One-Lane PHY for SS 14 LPP Databook (PHY Version: … ( PDF | HTML ) Release Notes DesignWare Cores PCIe 4.0 One-Lane PHY for SS 14 LPP Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_SS_14LPP_x1 |
| Product Code: | E096-0 |
| Description: | PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc12ffc_x16ns |
| Version: | 1.03b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databook DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 12 FFC Databook (PHY … ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Sixteen-Lane PHY for TSMC FFC Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_12FFC_x16 |
| Product Code: | C667-0 |
| Description: | PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc12ffc_x2ns |
| Version: | 1.03b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databook DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 12 FFC Databook (PHY … ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 12 FFC Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_12FFC_x2 |
| Product Code: | C736-0 |
| Description: | PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc12ffc_x4ns |
| Version: | 1.06a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.15) ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 12 FFC Databook (PHY … ( HTML | PDF ) DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 12 FFC Databook (PHY … ( PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Databook (PCS Version: 1.41) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 12 FFC Release Notes (PHY … ( TXT ) |
| Download: | dwc_pcie4phy_tsmc12ffc_x4ns |
| Product Code: | C727-0 |
| Description: | PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc16ffpgl_x16ns |
| Version: | 1.03a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11) ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Sixteen-Lane PHY for TSMC 16 FFPGL Databook (PHY … ( PDF ) DesignWare Cores PCIe 4.0 Sixteen-Lane PHY for TSMC 16 FFPGL Registers with … ( PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare Cores Multi-Protocol 16G PHY Sixteen-Lane for TSMC 16 FFPGL … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_16FFPGL_x16 |
| Product Code: | C365-0 |
| Description: | PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc16ffpgl_x4ns |
| Version: | 1.03a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores 25G PHY IP Integration Review Checklist Application Note (Doc … ( PDF | HTML ) DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11) ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Databook (PHY … ( PDF ) DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Registers with … ( PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_16FFPGL_x4 |
| Product Code: | B894-0 |
| Description: | PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc16ffpgl_x8ns |
| Version: | 1.03a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores 25G PHY IP Integration Review Checklist Application Note (Doc … ( PDF | HTML ) DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11) ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Eight-Lane PHY for TSMC 16 FFPGL Databook (PHY … ( PDF ) DesignWare Cores PCIe 4.0 Eight-Lane PHY for TSMC 16 FFPGL Registers with … ( PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare Cores Multi-Protocol 16G Eight-Lane PHY for TSMC 16 FFPGL Release … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_16FFPGL_x8 |
| Product Code: | B895-0 |
| Description: | PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc28hpcp_x2ns |
| Version: | 3.02b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 28 HPCP Databook (PHY … ( HTML | PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Databook (April 20, 2018) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 28 HPCP Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_28HPCP_x2 |
| Product Code: | D478-0 |
| Description: | PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc28hpcp_x4ns |
| Version: | 3.02b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.11) ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 PHY x4 for TSMC 28 HPCP Databook (PHY Version: 3.02b) ( PDF | HTML ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Databook (April 20, 2018) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 28 HPCP Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_28HPCP_x4 |
| Product Code: | C503-0 |
| Description: | PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc16ffc_x2ns |
| Version: | 1.03b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 16 FFC Databook (PHY Version … ( PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY (November 28, 2017) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Two-Lane PHY for TSMC 16 FFC Release Notes (PHY … ( TXT ) |
| Download: | PCIe-40-PHY_TSMC_16FFC_x2 |
| Product Code: | C665-0 |
| Description: | PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc16ffc_x4ns |
| Version: | 1.08a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 16G PHY IP Integration Review Checklist Application Note (Doc … ( PDF ) DesignWare Cores 25G PHY IP Integration Review Checklist Application Note (Doc … ( PDF | HTML ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PCIe 4.0 PHY ATE Testbench (Doc Version: 1.15) ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) DesignWare Cores PHY External SRAM Interface and Firmware Loading ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFC Databook (PHY … ( PDF | HTML ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Databook (PCS Version: 1.41) ( PDF ) Release Notes DesignWare Cores PCIe 4.0 Four-Lane PHY for TSMC FFC Release Notes (PHY … ( TXT ) |
| Download: | dwc_pcie4phy_tsmc16ffc_x4ns |
| Product Code: | C159-0 |
| Description: | PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc7ff_x2ns |
| Version: | 1.09a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | dwc_pcie4phy_tsmc7ff_x2ns |
| Product Code: | E125-0 |
| Description: | PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie4phy_tsmc7ff_x4ns |
| Version: | 1.10a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Application Notes DesignWare Cores 25G PHY IP Integration Review Checklist Application Note (Doc … ( PDF | HTML ) DesignWare Cores High Speed SerDes Custom Clock Grouping ( PDF ) DesignWare Cores High Speed SerDes Gate-Level Simulations ( PDF ) DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.30) ( PDF ) DesignWare Cores PCIe4 PHY ATE Testbench (Doc Version: 0.10) ( PDF ) DesignWare Cores PHY External ROM and External SRAM Interfaces and … ( PDF ) SerDes PCB and Packaging Design Guide ( PDF ) Databooks DesignWare Cores PCIe4 Four-Lane PHY for TSMC 7FF Databook (PHY Version: 1.10a) ( HTML | PDF ) PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY (Doc Version: 1.34) ( PDF ) Release Notes DesignWare Cores PCIe4 Four-Lane PHY for TSMC 7FF Release Notes (PHY … ( TXT ) |
| Download: | dwc_pcie4phy_tsmc7ff_x4ns |
| Product Code: | C417-0 |