The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.

Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.

Synopsys PHY IP for PCI Express 4.0 Datasheet

Highlights

Products

Downloads and Documentation

Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
Supports lane margining at the receiver
L1 substate and SRIS support
Power gating and power island
Embedded bit error rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40C to 125C junction temperatures
Supports flip-chip packaging

PCIe 4.0 LP PHY, TSMC N7 x1, North/South (vertical) poly orientation for Automotive	STARs	Subscribe
20G PHY for PCIe 4 PHY, GF12LPP 1.8V x4, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMC N5 1.2V x1, North/South (vertical) poly orientation	STARs	Subscribe
20G PHY for PCIe 4 PHY, TSMC5FF 1.2V x2, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N5, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, GF 12LP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS14LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC N7 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N6 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N6 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N6 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 LP PHY, TSMC N7 x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G PHY for Differential Buffer, TSMC N5, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc5ff_ns
Version:	3.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer for TSMC 5FF (PHY Version:3.07a_d1) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 5FF (PHY Version: 3.07a) ( TXT )
Download:	dwc_diffbuf_tsmc5ff_ns
Product Code:	F690-0

Description:	10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc7ff_ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer Databook for TSMC 7FF (PHY Version: 2.09a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 7FF (PHY Version: 2.09a) ( TXT )
Download:	dwc_diffbuf_tsmc7ff_ns
Product Code:	C522-0

Description:	20G PHY for PCIe 4 PHY, GF12LPP 1.8V x4, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_gf12lpp18_x4ns
Version:	2.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.30a) ( PDF \| HTML ) DesignWare SerDes PCB and Packaging Design Guide (Doc Version: 2.10a) ( PDF ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY (PCS Version: 1.47v) ( HTML \| PDF ) DesignWare Cores PCIe4 PHY for GF12 LPP (PHY Version: 2.03a) ( HTML \| PDF ) Release Notes DesignWare Cores PCIe4 PHY for GF12 LPP Release Notes (PHY Version: 2.03a) ( TEXT )
Download:	dwc_c20pcie4phy_gf12lpp18_x4ns
Product Code:	F972-0

Description:	20G PHY for PCIe 4 PHY, TSMC N5 1.2V x1, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc5ff12_x1ns
Version:	2.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform (Doc Version: 1.02a) ( PDF ) DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) DesignWare SerDes PCB and Packaging Design Guide (Doc Version: 2.10a) ( PDF ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY (PCS Version: 1.47s) ( PDF \| HTML ) DesignWare Cores PCIe4 x1 PHY for TSMC 5 FF (PHY Version: 2.07a) ( PDF \| HTML ) Release Notes DesignWare Cores PCIe4 x1 PHY for TSMC 5 FF Release Notes (PHY Version: 2.07a) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc5ff12_x1ns
Product Code:	E460-0

Description:	20G PHY for PCIe 4 PHY, TSMC5FF 1.2V x2, North/South (vertical) poly orientation
Name:	dwc_c20pcie4phy_tsmc5ff12_x2ns
Version:	2.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Compilation Using the LC and FC End-User Platform (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare Cores PCIe4 PHY ATE Test Bench (Doc Version: 0.40a) ( PDF \| HTML ) DesignWare SerDes PCB and Packaging Design Guide (Doc Version: 2.10a) ( PDF ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) Databooks Consumer 20 PCIe4 PCS for the DesignWare Cores Consumer 20 PCIe4 PHY (PCS Version: 1.47t) ( PDF \| HTML ) DesignWare Cores PCIe4 x2 PHY for TSMC5FF (PHY Version: 2.07a) ( PDF ) Release Notes DesignWare Cores PCIe4 x2 PHY for TSMC 5 FF Release Notes (PHY Version: 2.07a) ( TEXT )
Download:	dwc_c20pcie4phy_tsmc5ff12_x2ns
Product Code:	E461-0

Description:	PCIe 4.0 LP PHY, TSMC N6 x1, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc6ff_x1ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.60a) ( PDF \| HTML ) DesignWare® Cores SerDes PCB and Packaging Design Guide (Doc Version: 2.20a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x1 for TSMC 6FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY One-Lane (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x1 for TSMC 6FF Release Notes (PHY Version: 1.05a) ( TXT )
Download:	dwc_pcie4_lp_phy_tsmc6ff_x1ns
Product Code:	E989-0

Description:	PCIe 4.0 LP PHY, TSMC N6 x2, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc6ff_x2ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.60a) ( PDF \| HTML ) DesignWare® Cores SerDes PCB and Packaging Design Guide (Doc Version: 2.20a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY x2 (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 6FF Release Notes (PHY Version: 1.05a) ( TXT )
Download:	dwc_pcie4_lp_phy_tsmc6ff_x2ns
Product Code:	E990-0

Description:	PCIe 4.0 LP PHY, TSMC N6 x4, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc6ff_x4ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.60a) ( PDF \| HTML ) DesignWare® Cores SerDes PCB and Packaging Design Guide (Doc Version: 2.20a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 6FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY x4 (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 6FF Release Notes (PHY Version: 1.05a) ( TXT )
Download:	dwc_pcie4_lp_phy_tsmc6ff_x4ns
Product Code:	E991-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x1, North/South (vertical) poly orientation for Automotive
Name:	dwc_ap_pcie4_lp_phy_tsmc7ff_x1ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.60a) ( PDF \| HTML ) DesignWare® Cores SerDes PCB and Packaging Design Guide (Doc Version: 2.20a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP AP PHY x1 for TSMC 7FF Databook (PHY Version: 1.05a) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY One-Lane (PCS Version: 1.54a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP AP PHY x1 for TSMC 7FF Release Notes (PHY Version: 1.05a) ( TXT )
Download:	dwc_ap_pcie4_lp_phy_tsmc7ff_x1ns
Product Code:	H670-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc7ff_x2ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores Compilation Using the LC and FC End-User Platform 16G LP (Doc Version: 1.00a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.60a) ( PDF \| HTML ) DesignWare® Cores SerDes PCB and Packaging Design Guide (Doc Version: 2.20a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 7FF Databook (PHY Version: 1.05b) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.55a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x2 for TSMC 7FF Release Notes (PHY Version: 1.05b) ( TXT )
Download:	dwc_pcie4_lp_phy_tsmc7ff_x2ns
Product Code:	E231-0

Description:	PCIe 4.0 LP PHY, TSMC N7 x4, North/South (vertical) poly orientation
Name:	dwc_pcie4_lp_phy_tsmc7ff_x4ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G LP PHY Hardware Emulation (Doc Version: 2.00a) ( PDF \| HTML ) DesignWare® Cores 16G LP PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a_d1) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 LP PHY ATE Testbench (Doc Version: 1.60a) ( PDF \| HTML ) DesignWare® Cores SerDes PCB and Packaging Design Guide (Doc Version: 2.20a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 7FF Databook (PHY Version: 1.05b) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.48a, March 26, 2021) ( PDF \| HTML ) PCIe4 LP PCS for the DesignWare® Cores PCIe4 LP PHY (PCS Version: 1.54a_d1) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 7FF Release Notes (PHY Version: 1.01a_C4) ( TXT ) DesignWare® Cores PCIe 4.0 LP PHY x4 for TSMC 7FF Release Notes (PHY Version: 1.05b) ( TXT )
Download:	dwc_pcie4_lp_phy_tsmc7ff_x4ns
Product Code:	E232-0

Description:	PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x4ns
Version:	1.05b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist (Doc Version: 1.00) ( PDF ) DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.15a) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading (Doc Version: 1.00) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 14 LPP Databook (PHY Version: 1.05b) ( HTML \| PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (PCS Version: 1.41) ( HTML \| PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 14 LPP Release Notes (PHY Version: 1.05b) ( TXT )
Download:	dwc_pcie4phy_ss14lpp_x4ns
Product Code:	C998-0

Description:	PCIe 4.0 PHY, GF 12LP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_gf12lp_x4ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version:3.0) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe4 PHY for GF 12LP x4 Databook (PHY Version: 1.01a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (PCS Version: 1.41, July 27, 2020) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 PHY x4 for GF 12LP Release Notes (PHY Version: 1.01a) ( TXT )
Download:	dwc_pcie4phy_gf12lp_x4ns
Product Code:	E414-0

Description:	PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss11lpp_x1ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie4phy_ss11lpp_x1ns
Product Code:	E150-0

Description:	PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss11lpp_x2ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie4phy_ss11lpp_x2ns
Product Code:	E151-0

Description:	PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss11lpp_x4ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databook DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 11 LPP Databook (PHY Version: 1.00a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for SS 11 LPP Release Notes (PHY Version: 1.00a) ( TXT )
Download:	PCIe-40-PHY_SS_11LPP_x4
Product Code:	E101-0

Description:	PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x2ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe 4.0 Two-Lane PHY for SS 14 LPP Databook (PHY Version: 1.05a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for SS 14 LPP Release Notes (PHY Version: 1.05a) ( TXT )
Download:	PCIe-40-PHY_SS_14LPP_x2
Product Code:	E097-0

Description:	PCIe 4.0 PHY, SS14LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x1ns
Version:	1.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) Databook DesignWare® Cores PCIe 4.0 One-Lane PHY for SS 14 LPP Databook (PHY Version: 1.05a) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 One-Lane PHY for SS 14 LPP Release Notes (PHY Version: 1.05a) ( TXT )
Download:	PCIe-40-PHY_SS_14LPP_x1
Product Code:	E096-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x16ns
Version:	1.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databook DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 12FFC x2 Databook (PHY Version: 1.06b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Sixteen-Lane PHY for TSMC FFC Release Notes (PHY Version: 1.03b) ( TXT )
Download:	PCIe-40-PHY_TSMC_12FFC_x16
Product Code:	C667-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x2ns
Version:	1.06b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.15a) ( HTML \| PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 12FFC x2 Databook (PHY Version: 1.06b) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (April 15, 2021) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 12FFC x2 Release Notes (PHY Version: 1.06b) ( TXT )
Download:	dwc_pcie4phy_tsmc12ffc_x2ns
Product Code:	C736-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x4ns
Version:	1.06b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.15a) ( PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 12 FFC Databook (PHY Version: 1.06b_d1) ( PDF \| HTML ) DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 12FFC x2 Databook (PHY Version: 1.06b) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (PCS Version: 1.41) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 12 FFC Release Notes (PHY Version: 1.06b) ( TXT )
Download:	dwc_pcie4phy_tsmc12ffc_x4ns
Product Code:	C727-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x16ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11a) ( PDF ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Sixteen-Lane PHY for TSMC 16 FFPGL Databook (PHY Version: 1.03a) ( PDF ) DesignWare® Cores PCIe 4.0 Sixteen-Lane PHY for TSMC 16 FFPGL Registers with Change Bars (PHY Version: 1.03a) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare® Cores Multi-Protocol 16G PHY Sixteen-Lane for TSMC 16 FFPGL Release Notes (PHY Version: 1.03a) ( TXT )
Download:	PCIe-40-PHY_TSMC_16FFPGL_x16
Product Code:	C365-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11a) ( PDF ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading (Doc Version: 1.00) ( PDF \| HTML ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Databook (PHY Version: 1.03a) ( PDF ) DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Registers with Change Bars (PHY Version: 1.03a) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFPGL Release Notes (PHY Version: 1.03a) ( TXT )
Download:	PCIe-40-PHY_TSMC_16FFPGL_x4
Product Code:	B894-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x8ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench (Doc Version: 1.11a) ( PDF ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores Multi-Protocol 16G PHY RX Internal Eye Monitor (February 2017) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading (Doc Version: 1.00) ( PDF \| HTML ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Eight-Lane PHY for TSMC 16 FFPGL Databook (PHY Version: 1.03a) ( PDF ) DesignWare® Cores PCIe 4.0 Eight-Lane PHY for TSMC 16 FFPGL Registers with Change Bars (PHY Version: 1.03a) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (February 7, 2018) ( PDF ) Release Notes DesignWare® Cores Multi-Protocol 16G Eight-Lane PHY for TSMC 16 FFPGL Release Notes (PHY Version: 1.03a) ( TXT )
Download:	PCIe-40-PHY_TSMC_16FFPGL_x8
Product Code:	B895-0

Description:	PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc28hpcp_x2ns
Version:	3.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 28 HPCP Databook (PHY Version: 3.02b) ( HTML \| PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (April 20, 2018) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 28 HPCP Release Notes (PHY Version: 3.02b) ( TXT )
Download:	PCIe-40-PHY_TSMC_28HPCP_x2
Product Code:	D478-0

Description:	PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc28hpcp_x4ns
Version:	3.02b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.11) ( PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 PHY x4 for TSMC 28 HPCP Databook (PHY Version: 3.02b) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (April 20, 2018) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 28 HPCP Release Notes (PHY Version: 3.02b) ( TXT )
Download:	PCIe-40-PHY_TSMC_28HPCP_x4
Product Code:	C503-0

Description:	PCIe 4.0 PHY, TSMC N7 x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x1ns
Version:	1.13a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
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Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version: 0.30a) ( PDF ) Databooks DesignWare® Cores PCIe4 Single-Lane PHY for TSMC 7FF Databook (PHY Version: 1.13a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x1 (Doc Version: 1.51b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 Single-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TXT )
Download:	dwc_pcie4phy_tsmc7ff_x1ns
Product Code:	E202-0

Description:	PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x1ns
Version:	1.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.15a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 One-Lane PHY for TSMC 16FFC x1 Databook (PHY Version 1.08a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (March 26, 2021) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe 4.0 One-Lane PHY for TSMC 16FFC x1 Release Notes (PHY Version: 1.08a) ( TXT )
Download:	dwc_pcie4phy_tsmc16ffc_x1ns
Product Code:	E200-0

Description:	PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x2ns
Version:	1.03b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 16 FFC Databook (PHY Version 1.03b) ( PDF ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (November 28, 2017) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Two-Lane PHY for TSMC 16 FFC Release Notes (PHY Version 1.03b) ( TXT )
Download:	PCIe-40-PHY_TSMC_16FFC_x2
Product Code:	C665-0

Description:	PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x4ns
Version:	1.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 16G PHY IP Integration Review Checklist Application Note (Doc Version: 1.01a) ( PDF \| HTML ) DesignWare® Cores 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PCIe 4.0 PHY ATE Testbench Application Note (Doc Version: 1.15a) ( HTML \| PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading (Doc Version: 1.00) ( PDF \| HTML ) DesignWare® Cores PHY – External SRAM Interface and Firmware Loading (Doc Version: 3.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC 16 FFC Databook (PHY Version: 1.08a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY Databook (PCS Version: 1.41) ( PDF ) Release Notes DesignWare® Cores PCIe 4.0 Four-Lane PHY for TSMC FFC Release Notes (PHY Version: 1.08a) ( TXT )
Download:	dwc_pcie4phy_tsmc16ffc_x4ns
Product Code:	C159-0

Description:	PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x2ns
Version:	1.13a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version: 0.30a) ( PDF \| HTML ) Databooks DesignWare® Cores PCIe4 Two-Lane PHY for TSMC 7FF Databook (PHY Version: 1.13a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY (Doc Version: 1.51b) ( HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x2 (Doc Version: 1.51b) ( PDF ) Release Notes DesignWare® Cores PCIe4 Two-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TXT )
Download:	dwc_pcie4phy_tsmc7ff_x2ns
Product Code:	E125-0

Description:	PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x4ns
Version:	1.13a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare® Cores 25G PHY IP Integration Review Checklist Application Note (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Custom Clock Grouping (Doc Version: 1.10a) ( PDF \| HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.10a) ( HTML ) DesignWare® Cores High Speed SerDes Gate-Level Simulations (Doc Version: 1.11a) ( PDF ) DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version: 0.20a) ( HTML ) DesignWare® Cores PCIe4 PHY ATE Testbench (Doc Version: 0.30a) ( PDF ) DesignWare® Cores PHY – External ROM and External SRAM Interfaces and Firmware Loading (Doc Version: 1.00) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.30a) ( HTML \| PDF ) Databooks DesignWare® Cores PCIe4 Four-Lane PHY for TSMC 7FF Databook (PHY Version: 1.13a) ( PDF \| HTML ) PCIe 4.0 PCS for the DesignWare® Cores PCIe 4.0 PHY x4 (Doc Version: 1.51b) ( PDF \| HTML ) Release Notes DesignWare® Cores PCIe4 Four-Lane PHY for TSMC 7FF Release Notes (PHY Version: 1.13a) ( TXT )
Download:	dwc_pcie4phy_tsmc7ff_x4ns
Product Code:	C417-0