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DesignWare PHY IP for PCI Express 4.0
The multi-channel DesignWare® PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.
The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
DesignWare IP for PCI Express Complete Solution Datasheet DesignWare PHY IP for PCI Express 4.0 Datasheet
Highlights
Products
Downloads and Documentation
- Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- Supports lane margining at the receiver
- L1 substate and SRIS support
- Power gating and power island
- Embedded bit error rate (BER) tester and internal eye monitor
- Built-in Self Test vectors, PRBS generation and checker
- IEEE 1149.6 AC JTAG Boundary Scan
- Supports -40C to 125C junction temperatures
- Supports flip-chip packaging
| PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation | STARs | Subscribe |
