DesignWare PHY IP for PCI Express 4.0

The multi-channel DesignWare® PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support.

Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.

DesignWare IP for PCI Express Complete Solution Datasheet
DesignWare PHY IP for PCI Express 4.0 Datasheet

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Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
Supports lane margining at the receiver
L1 substate and SRIS support
Power gating and power island
Embedded bit error rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40C to 125C junction temperatures
Supports flip-chip packaging

PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation	STARs	Subscribe

Description:	PCIe 4.0 PHY, SS14LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_ss14lpp_x4ns
Version:	1.00a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe 4.0 PHY ATE Test Bench DesignWare Cores PHY External ROM and External SRAM Interfaces and … SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for SS 14 LPP PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for SS 14 LPP
Download:	PCIe-40-PHY_SS_14LPP_x4
Product Code:	C998-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x16, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x16ns
Version:	1.03b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe 4.0 PHY ATE Test Bench DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 12 FFC PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC FFC
Download:	PCIe-40-PHY_TSMC_12FFC_x16
Product Code:	C667-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x2ns
Version:	1.03b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe 4.0 PHY ATE Test Bench DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 12 FFC PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC FFC
Download:	PCIe-40-PHY_TSMC_12FFC_x2
Product Code:	C736-0

Description:	PCIe 4.0 PHY, TSMC 12FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc12ffc_x4ns
Version:	1.03b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe 4.0 PHY ATE Test Bench DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 12 FFC PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC FFC
Download:	PCIe-40-PHY_TSMC_12FFC_x4
Product Code:	C727-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x16, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x16ns
Version:	1.03a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores Multi-Protocol 16G PHY RX Internal Eye Monitor DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 16 FFPGL PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Register databook with change bars Release Notes DesignWare Cores Multi-Protocol 16G PHY for TSMC 16 FFPGL
Download:	PCIe-40-PHY_TSMC_16FFPGL_x16
Product Code:	C365-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x4ns
Version:	1.03a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores Multi-Protocol 16G PHY RX Internal Eye Monitor DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 16 FFPGL PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Register databook with change bars Release Notes DesignWare Cores Multi-Protocol 16G PHY for TSMC 16 FFPGL
Download:	PCIe-40-PHY_TSMC_16FFPGL_x4
Product Code:	B894-0

Description:	PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffpgl_x8ns
Version:	1.03a
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores Multi-Protocol 16G PHY RX Internal Eye Monitor DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 16 FFPGL PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Register databook with change bars Release Notes DesignWare Cores Multi-Protocol 16G PHY for TSMC 16 FFPGL
Download:	PCIe-40-PHY_TSMC_16FFPGL_x8
Product Code:	B895-0

Description:	PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc28hpcp_x2ns
Version:	3.01b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores PCIe 4.0 PHY ATE Test Bench SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 28 HPCP PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC 28 HPCP
Download:	PCIe-40-PHY_TSMC_28HPCP_x2
Product Code:	D478-0

Description:	PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc28hpcp_x4ns
Version:	3.01b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe 4.0 PHY ATE Test Bench DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 28 HPCP PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC 28 HPCP
Download:	PCIe-40-PHY_TSMC_28HPCP_x4
Product Code:	C503-0

Description:	PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x2ns
Version:	1.03b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe 4.0 PHY ATE Test Bench DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe 4.0 PHY for TSMC 16 FFC PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC FFC
Download:	PCIe-40-PHY_TSMC_16FFC_x2
Product Code:	C665-0

Description:	PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc16ffc_x4ns
Version:	1.02c
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores Enterprise 16G PCIe 4.0 PHY ATE Test Bench DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PHY External SRAM Interface and Firmware Loading SERDES PCB and Packaging Design Guide Databooks Current databook with change bars DesignWare Cores PCIe 4.0 PHY for TSMC 16 FFC PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe 4.0 PHY for TSMC FFC
Download:	PCIe-40-PHY_TSMC_16FFC_x4
Product Code:	C159-0

Description:	PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
Name:	dwc_pcie4phy_tsmc7ff_x4ns
Version:	1.09b
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare Cores High Speed SerDes Custom Clock Grouping DesignWare Cores High Speed SerDes Gate-Level Simulations DesignWare Cores PCIe4 PHY ATE Testbench DesignWare Cores PHY External ROM and External SRAM Interfaces and … SERDES PCB and Packaging Design Guide Databooks DesignWare Cores PCIe4 PHY for TSMC 7FF PCIe 4.0 PCS for the DesignWare Cores PCIe 4.0 PHY Release Notes DesignWare Cores PCIe4 PHY for TSMC 7FF
Download:	PCIe-40-PHY_TSMC_N7_x4
Product Code:	C417-0

DesignWare PHY IP for PCI Express 4.0

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