VC Verification IP for SPI/QSPI

Synopsys VC Verification IP for Serial Peripheral Interface and (SPI Flash) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of SPI based designs.

SPI/QSPI VC Verification IP

Protocol Features

  • Supports Motorola S12SP1V3/D SPI Block Guide V03.06
  • Multi I/O, 8 lane support (Dual/Quad and Octal)
  • Master and Slave Configurations
  • All SPI operating modes
  • Register Data Width (8/16/32)
  • Bit and Byte Endianness
  • Payload size control and data value control
  • Baud rate control for Master Agent
  • Data Transfer Modes (Transmit and Receive, Tx Only, Rx Only, and EEPROM)
  • Configurable length for Instruction, Address, and Data Phase
  • Configurable lane count for Instruction, Address, and Data Phase
  • Configurable timers (Leading, Trailing, and Idle time between transfer)