Custom Design Formal Equivalence Checking Based on Symbolic Simulation

ESP is an equivalence checker for full custom designs. It enables efficient comparison of a Verilog reference design against other Verilog models or a transistor-level SPICE netlist.

ESP provides fast and extensive coverage, enabling users to quickly find bugs and have the confidence that the Verilog reference design is functionally identical to other Verilog models or its transistor-level implementation. ESP improves overall verification productivity by simplifying the testing process. It directly verifies the SPICE netlist, eliminating the need to manually extract the transistor network into a gate-level representation.


  • Fast and broad coverage quickly finds bugs yielding higher quality
  • Supports new device technologies through Device Model Simulation and increases productivity
  • Directly verifies the SPICE netlist, eliminating the need for gate-level abstraction
ESP-CV Fills the Verification Gap

Bridging the verification gap between Verilog and SPICE