Cloud Computing Networking

Traditional data centers use a tiered network topology consisting of switched Ethernet with VLAN tagging. This topology only defines one path to the network, which has traditionally handled north-south data traffic. The transition to a flat, two-tier leaf-spine hyperscale data center network using up to 800G Ethernet links enables virtualized servers to distribute workflows among many virtual machines, creating a faster, more scalable cloud data center environment.

Smart network interface cards (NICs) combine hardware, programmable AI acceleration, and security resources to offload server processors, freeing the processors to run applications. Integrated security, including a root of trust, protects coefficient and biometric data as it moves to and from local memories. Smart NICs accelerate embedded virtual switch, transport offloads, and protocol overlay encapsulation/decapsulation such as NVGRE, VXLAN and MPLS. By offering dedicated hardware offloads including NVMe-over-Fabric (NVMe-oF) protocols, Smart NICs free the server CPU to focus compute cycles on cloud application software and enable efficient data sharing across nodes for HPC workloads. 

Network switch SoCs enable cloud data center top-of-rack and end-of-row switches and routers to scale port densities and speeds to quickly adapt to changing cloud application workloads. To scale port speeds from 10Gb Ethernet to 400/800G Ethernet and extend port densities from dozens to hundreds of ports, the latest generation Ethernet switch SoCs must scale to provide lowest latency and highest throughput flow control and traffic management. 

Synopsys’ IP portfolio supports widely used interfaces such as HBI and USR/XSR die-to-die, Ethernet, PCI Express, CXL, CCIX, USB, DDR, and HBM2/2E. Synopsys Interface IP is optimized to help designers meet the high-throughput, low-latency connectivity needs of cloud computing networking applications. Synopsys’ Foundation IP offers configurable embedded memories for performance, power, and area, as well as high-speed logic libraries for all processor cores.