Cloud Computing Networking

Traditional data centers use a tiered network topology consisting of switched Ethernet with VLAN tagging. This topology only defines one path to the network, which has traditionally handled north-south data traffic. The transition to a flat, two-tier leaf-spine hyperscale data center network using up to 400G Ethernet links enables virtualized servers to distribute workflows among many virtual machines, creating a faster, more scalable cloud data center environment. Software defined network (SDN) where the control is decoupled from the data path allows a common software stack such as OpenFlow to provide a consistent industry-wide control software environment. Instead of having a proprietary software stack, designers have an OpenFlow managed network, allowing users to provision the networks very easily (virtually), without requiring physical access to the network's hardware devices. Synopsys’ DesignWare interface IP portfolio supporting high-performance protocols such as Ethernet, PCI Express, CCIX, USB, DDR, and HBM, are optimized to help designers meet their high-throughput, low-latency connectivity needs of cloud computing networking applications. Synopsys’ foundation IP offers configurable embedded memories for performance, power, and area, as well as high-speed logic libraries for all processor cores.

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DDR5/4 Controller and PHY

  • Scalable DDR architecture supporting up to 4800 Mbps with single and dual channels
  • High-performance multi-standard PHY
  • High-bandwidth and low latency controller
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Ethernet Controller and PHY

  • Complete solution for up to 400G Ethernet applications
  • Configurable Ethernet controllers compliant with IEEE standards
  • High-performance, multi-standard NRZ and PAM-4 PHYs enable required reach and performance
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PCIe Controller and PHY

  • High-performance, multi-channel PCIe PHY supporting PCIe 5.0, 4.0, 3.1, 2.1, 1.1
  • Configurable PCIe controller supporting PCIe 5.0, 4.0, 3.1, 2.1, 1.1
  • Up to 16 lanes PCIe Dual Mode/Switch Port controller with SR-IOV and RAS features
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AMBA Interconnect

  • ARM® AMBA® 4 AXI, ACE-Lite™, AXI3™, AHB™, APB™ interconnect IP
  • Automated AMBA subsystem assembly
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Embedded Memories and Logic Libraries

  • High-speed and high-density memory compilers and logic libraries
  • Optimized for advanced CPUs, GPUs, and DSPs
  • High Performance Core Design Kit for optimal processor speed, area and power
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