Welcome to the latest issue of the ASIP eUpdate Newsletter, our bi-annual publication to keep you informed on technical topics related to application-specific instruction-set processor (ASIP) design. In the previous two newsletters, we covered some example models that are provided with ASIP Designer. Judging from your feedback, this topic seems to be of high interest, so we decided to give even more room to it this time. The other main topic is an update on the 2016.09 release of ASIP Designer. We hope you enjoy today’s issue, and we look forward to your feedback and suggestions.
ASIPs are a proven solution for domain-specific/application-optimized processors, plus often serve as a more flexible yet equally efficient alternative to fixed RTL implementations, often referred to as programmable accelerators. ASIPs come with an architecture and instruction set tuned for a specific application domain. They rely on techniques similar to those used in the design of hardware accelerators to reach high performance and low power: heavy use of parallelism and specialized datapath elements. Yet ASIPs retain software programmability within their application domain, resulting in C/C++ programmable processors and accelerators with the lowest power possible.